公开(公告)号：US10957381B1

公开(公告)日：2021-03-23

申请号：US16553358

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G11C7/10 ,  G11C11/409 ,  G06F12/02 ,  G06F3/06 ,  G06F13/16

Abstract: Devices and techniques are disclosed herein to address high latency associated with large-scale un-map or trim commands associated with flash memory. In an example, a method can include receiving a trim command for a partition of a storage system, identifying a record of a partition table of the storage system corresponding to the partition, updating a partition count of the record with a count value of a partition counter of the storage system, and incrementing the partition counter.

公开(公告)号：US20210073070A1

公开(公告)日：2021-03-11

申请号：US17099389

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Jonathan Scott Parry ,  Nadav Grosz ,  David Aaron Palmer ,  Christian M. Gyllenskog

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/02

Abstract: Apparatus and methods are disclosed, including using a memory controller to monitor at least one parameter related to power level of a host processor of a host device, and dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device.

公开(公告)号：US20210065768A1

公开(公告)日：2021-03-04

申请号：US16554247

申请日：2019-08-28

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G11C11/409 ,  G06F12/02 ,  G06F12/14 ,  G06F3/06

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a flash storage system. In an example, read commands or write commands can optionally include a file-type indicator. The file-type indicator can allow for exchange of data between the host and the flash storage system using a single record of a Flash Translation Layer (FTL) table or logical-to-physical (L2P) table, and where the amount of data can be much larger than the atomic unit associated with the flash storage system.

公开(公告)号：US10754726B2

公开(公告)日：2020-08-25

申请号：US16107187

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F11/10 ,  G06F16/901

Abstract: Aspects of the present disclosure configure a memory sub-system to track error-correction parity calculations in the memory sub-system. For example, a memory sub-system controller of the memory sub-system can generate and use a first data structure to map one or more data chunks of an open data block to one or more buffers in a set of buffers for temporary storage of partial parity calculation results for the one or more data chunks, and generate and use a second data structure to map one or more data chunks of an open data block to one or more memory locations on non-volatile memory space (implemented by a set of memory components) for persistent storage of partial panty calculation results for the one or more data chunks.

公开(公告)号：US10725930B2

公开(公告)日：2020-07-28

申请号：US16113014

申请日：2018-08-27

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/10 ,  G06F16/22

Abstract: Aspects of the present disclosure configure a memory sub-system to map logical memory addresses to physical memory addresses using a tree data structure in the memory sub-system. For example, a memory sub-system controller of the memory sub-system can generate a tree data structure on cache memory to cache, from non-volatile memory, at least one portion of mapping data, where the non-volatile memory is implemented by a set of memory components separate from the cache memory. The mapping data, stored on the non-volatile memory, can map a set of logical memory addresses to a corresponding set of physical memory addresses of the non-volatile memory, and a node of the tree data structure can comprise node data that describes a memory area of the non-volatile memory where data is written across a sequence of contiguous physical memory addresses.

公开(公告)号：US20200210283A1

公开(公告)日：2020-07-02

申请号：US16236094

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29 ,  G06F12/10

Abstract: Devices and techniques for extended error correction in a storage device are described herein. A first set of data, that has a corresponding logical address and physical address, is received. A second set of data can be selected based on the logical address. Secondary error correction data can be computed from the first set of data and the second set of data. Primary error correction data can be differentiated from the secondary error correction data by being computed from the first set of data and a third set of data. The third set of data can be selected based on the physical address of the first set of data. The secondary error correction data can be written to the storage device based on the logical address.

公开(公告)号：US20200210073A1

公开(公告)日：2020-07-02

申请号：US16236785

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

Abstract: Apparatus and methods are disclosed, including a controller circuit, a volatile memory, a non-volatile memory, and a reset circuit, where the reset circuit is configured to receive a reset signal from a host device and actuate a timer circuit. The timer circuit, where the timer circuit is configured to cause a storage device to reset after a threshold time period. The reset circuit is further configured to actuate the controller circuit to write data stored in the volatile memory to the non-volatile memory before the storage device is reset.

公开(公告)号：US20200167279A1

公开(公告)日：2020-05-28

申请号：US16201537

申请日：2018-11-27

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F12/0804

Abstract: Devices and techniques for enhanced flush transfer efficiency in a storage device are described herein. A flush trigger for a user data write can be identified. Here, user data corresponds to the user data write and was stored in a buffer. The size of the user data stored in the buffer is smaller than a write width for a storage device subject to the write. The difference ins the user data size in the buffer and the write width is buffer free space. Additional data can be marshalled in response to the identification of the flush trigger. Here, the additional data size is less than or equal to the buffer free space. The user data and the additional data can then be written to the storage device.

公开(公告)号：US20190384528A1

公开(公告)日：2019-12-19

申请号：US16010940

申请日：2018-06-18

Applicant: Micron Technology, Inc.

Inventor： Nadav Grosz ,  David Aaron Palmer

IPC: G06F3/06

Abstract: Devices and techniques for an adjustable watchdog in a memory device are disclosed herein. A memory operation command is received at a first time with a memory device from a host. A reset signal is received, with the memory device from the host, at a second time following the first time. A time interval between the first time and the second time is measured. A delay interval for a timer in the memory device to reset the memory device independently of receiving a further reset signal from the host is established based on the measured time interval.

公开(公告)号：US12271620B2

公开(公告)日：2025-04-08

申请号：US18521693

申请日：2023-11-28

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer

IPC: G06F3/06

Abstract: Methods, systems, and devices for techniques for improved write performance modes are described. A memory system and a host system may support a high performance mode to write data to the memory system. For example, the host system may provision a dedicated logical unit of the memory system. Upon detecting an urgent situation, the host system may transmit a command to the memory system to enter the high performance mode. In response to the command, the memory system may abort ongoing operations, such as internal memory management operations. Additionally, the host system and the memory system may configure operational parameters to increase the speed of write operations, such as a trim set for writing data to the logical unit, a bit rate of data transfer between the host system and the memory system, clock speeds of the memory system, or a combination thereof.