公开(公告)号：US10832754B1

公开(公告)日：2020-11-10

申请号：US16433871

申请日：2019-06-06

Applicant: Micron Technology, Inc.

Inventor： Kristen M. Hopper ,  Debra M. Bell ,  Aaron P. Boehm

IPC: G11C5/14 ,  G11C11/22 ,  G11C11/4074 ,  G06F11/34 ,  G06F11/30 ,  G11C11/4076

Abstract: Methods, systems, and devices for a current monitor for a memory device are described. A memory device may monitor potential degradation of memory cells on the device by monitoring the amount of current drawn by one or more memory cells. As the memory cells degrade, the current supplied to the memory cells may change (e.g., increase due to additional leakage current. The memory device may indirectly monitor changes in the current supplied to the memory cells by monitoring a voltage of a node of a transistor that controls the amount of current supplied to the array of memory cells. The voltage at the control node may be compared to a reference voltage to determine whether the two voltages differ by a threshold amount, indicating that the memory cells are drawing more current. The memory device may output a status indicator when the voltages differ, for example, by the threshold amount.

公开(公告)号：US10741566B2

公开(公告)日：2020-08-11

申请号：US16427176

申请日：2019-05-30

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell

IPC: H01L27/11 ,  G11C11/41 ,  G11C11/419 ,  G11C11/412 ,  H01L27/092

Abstract: Some embodiments include an integrated assembly having a first pull-down transistor, a second pull-down transistor, a first pull-up transistor and a second pull-up transistor. The first pull-down transistor has a first conductive-gate-body at a first level, and has an n-channel-device-active-region at a second level vertically offset from the first level. The first pull-up transistor has a second conductive-gate-body at the first level, and has a p-channel-device-active-region at the second level. The second pull-down transistor has a third conductive-gate-body at the second level, and has an n-channel-device-active-region at the first level. The second pull-up transistor has a fourth conductive-gate-body at the second level, and has a p-channel-device-active-region at the first level.

公开(公告)号：US20200211626A1

公开(公告)日：2020-07-02

申请号：US16237115

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Dale H. Hiscock ,  Debra M. Bell ,  Michael Kaminski ,  Joshua E. Alzheimer ,  Anthony D. Veches ,  James S. Rehmeyer

IPC: G11C11/4093 ,  G11C11/406 ,  G11C11/4096 ,  G11C5/02 ,  H01L25/10 ,  G11C7/18

Abstract: Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.

公开(公告)号：US20200058333A1

公开(公告)日：2020-02-20

申请号：US16103151

申请日：2018-08-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Debra M. Bell

IPC: G11C7/22 ,  G11C7/12 ,  G11C7/10 ,  G11C11/4076

Abstract: A write-in date circuit in a semiconductor device may include multiple input buffers, each receiving multiple data bits in a serial data stream. The circuit may include a first circuit coupled to a first and a second input buffers. The first circuit may be further coupled to receive a DQS signal and latch a first data bit selected from the first input buffer or the second input buffer responsive to the DQS signal. The second circuit may be coupled to the first and second input buffers and configured to latch a second data bit selected from the first input buffer or the second input buffer responsive to the DQS signal. The first circuit may latch the first data bit responsive to a rising edge of the DQS signal and the second circuit may latch the second data bit responsive to a falling edge of the DQS signal.

公开(公告)号：US20150055420A1

公开(公告)日：2015-02-26

申请号：US14010120

申请日：2013-08-26

Applicant: Micron Technology, Inc.

Inventor： Debra M. Bell ,  Jeff A. McClain ,  Brian P. Callaway

IPC: G11C11/406 ,  G11C7/10

CPC classification number: G11C11/406 ,  G11C7/1012

Abstract: Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.