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公开(公告)号：US20230395116A1
公开(公告)日：2023-12-07
申请号：US18202149
申请日：2023-05-25
发明人： Anthony D. Veches , Scott E. Smith
IPC分类号： G11C11/406
CPC分类号： G11C11/406
摘要： Methods, systems, and devices for techniques for flexible self-refresh of memory arrays are described. A memory system may set a respective refresh region for each respective memory bank of the memory system by tracking access to memory row addresses in respective memory banks used in the respective memory banks. For example, the memory system may monitor respective access commands issued to each respective memory bank and store information in a register of each respective memory bank. The memory system may determine whether a respective memory row address associated with a respective access command is within the respective refresh region and process the respective memory bank. The memory system may update a value stored in a register of the respective memory bank (e.g., a memory row address value) to adjust the refresh region of the respective memory bank without updating refresh regions for other memory banks in the memory system.
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公开(公告)号：US11682435B2
公开(公告)日：2023-06-20
申请号：US17811153
申请日：2022-07-07
发明人： Di Wu , Debra M. Bell , Anthony D. Veches , James S. Rehmeyer , Libo Wang
IPC分类号： G11C7/22 , G11C7/10 , G11C8/10 , G11C11/4096 , G11C11/4076 , G11C11/406
CPC分类号： G11C7/22 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C8/10 , G11C11/4076 , G11C11/4096 , G11C11/40603
摘要： Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.
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公开(公告)号：US11532349B2
公开(公告)日：2022-12-20
申请号：US17221498
申请日：2021-04-02
IPC分类号： G11C11/40 , G11C11/4074 , H01L25/065 , H01L25/00 , H01L23/00 , H01L23/525 , G11C11/22 , G06F13/16
摘要： Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.
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公开(公告)号：US20220334917A1
公开(公告)日：2022-10-20
申请号：US17854331
申请日：2022-06-30
发明人： Anthony D. Veches
IPC分类号： G06F11/10
摘要： Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.
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公开(公告)号：US11449267B1
公开(公告)日：2022-09-20
申请号：US17243357
申请日：2021-04-28
IPC分类号： G06F3/06
摘要： Methods, systems, and apparatuses related to determination of durations of memory device temperatures are described. For example, a controller can be coupled to a memory device to monitor an operating temperature of the memory device. The controller can determine the operating temperature exceeds a threshold temperature. The controller can determine a duration that the temperature exceeds the threshold temperature. The controller can provide data corresponding to the operating temperature and the duration to a requesting device.
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公开(公告)号：US20210295901A1
公开(公告)日：2021-09-23
申请号：US17338191
申请日：2021-06-03
发明人： Dale H. Hiscock , Debra M. Bell , Michael Kaminski , Joshua E. Alzheimer , Anthony D. Veches , James S. Rehmeyer
IPC分类号： G11C11/406 , G11C29/00 , G11C11/409 , G11C11/4074
摘要： Memory with partial bank refresh is disclosed herein. In one embodiment, a memory system includes a memory controller and a memory device operably connected to the memory controller. The memory device includes (i) a memory array having a memory bank with a plurality of memory cells arranged in a plurality of memory rows and (ii) circuitry. In some embodiments, the circuitry is configured to disable at least one memory row of the memory bank from receiving refresh commands such that memory cells of the at least one memory row are not refreshed during refresh operations of the memory device. In some embodiments, the memory controller is configured to track memory rows that include utilized memory cells and/or to write data to the memory rows in accordance with a programming sequence of the memory device.
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公开(公告)号：US11087829B2
公开(公告)日：2021-08-10
申请号：US16926476
申请日：2020-07-10
IPC分类号： G11C11/4094 , G11C11/408 , G11C11/4096 , G11C11/406
摘要： Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.
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公开(公告)号：US20210216397A1
公开(公告)日：2021-07-15
申请号：US17214684
申请日：2021-03-26
发明人： Anthony D. Veches
IPC分类号： G06F11/10
摘要： Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.
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公开(公告)号：US11024367B2
公开(公告)日：2021-06-01
申请号：US17017545
申请日：2020-09-10
发明人： Dale H. Hiscock , Debra M. Bell , Michael Kaminski , Joshua E. Alzheimer , Anthony D. Veches , James S. Rehmeyer
IPC分类号： G11C5/02 , G11C11/4093 , G11C11/406 , G11C7/18 , H01L25/10 , G11C11/4096
摘要： Memory devices and systems with on-die data transfer capability, and associated methods, are disclosed herein. In one embodiment, a memory device includes an array of memory cells and a plurality of input/output lines operably connecting the array to data pads of the device. In some embodiments, the memory device can further include a global cache and/or a local cache. The memory device can be configured to internally transfer data stored at a first location in the array to a second location in the array without outputting the data from the memory device. To transfer the data, the memory device can copy data on one row of memory cells to another row of memory cells, directly write data to the second location from the first location using data read/write lines of the input/output lines, and/or read the data into and out of the global cache and/or the local cache.
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公开(公告)号：US10963336B2
公开(公告)日：2021-03-30
申请号：US16554958
申请日：2019-08-29
发明人： Anthony D. Veches
IPC分类号： G06F11/10
摘要： Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.
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