公开(公告)号：US20060194137A1

公开(公告)日：2006-08-31

申请号：US11363262

申请日：2006-02-28

申请人： Hiromichi Kobayashi ,  Toru Iwata ,  Toshio Honjo

发明人： Hiromichi Kobayashi ,  Toru Iwata ,  Toshio Honjo

IPC分类号： G03G9/10

CPC分类号： G03G9/107 ,  G03G9/1132

摘要： It is contemplated to provide irregular shaped ferrite carrier which has a lower resistance, a high specific surface area, a low specific gravity and a longer operational life, and an electrophotographic developer comprising the ferrite carrier which prevents the toner scattering, has a high image density, and is responsive to high-speed and color imaging. The irregular shaped ferrite carrier is characterized in that the carrier particles are irregular shaped, and 40 percent by number or more of the particles have a rock candy sugar shape and/or an oyster shell shape, and that the shape factor (SF-1=R2/S×π/4×100, wherein R is a maximum length and S is a projected area.) is 140 to 250, and the distribution width (δ) is 60 or less.

摘要翻译： 考虑到提供具有较低电阻，高比表面积，低比重和较长使用寿命的不规则形状的铁氧体载体，以及包含防止调色剂飞散的铁氧体载体的电子照相显影剂具有高图像密度 ，并且响应于高速和彩色成像。 不规则形状的铁氧体载体的特征在于，载体颗粒是不规则形状，并且40个数量以上的颗粒具有岩糖糖糖形状和/或牡蛎壳形状，并且形状因子（SF-1 = 其中，R为最大长度，S为投影面积）为140〜250，分布宽度（delta）为60以下。

公开(公告)号：US20060097772A1

公开(公告)日：2006-05-11

申请号：US11188855

申请日：2005-07-26

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata

IPC分类号： G05F1/10

CPC分类号： H02M3/07

摘要： The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

摘要翻译： 电荷泵电路包括：第一开关，用于基于第一控制信号控制按压操作和拉动操作中的任一个; 由与第一开关属性不同的晶体管构成的电流镜电路; 以及由构成第一开关的晶体管的特性相同的晶体管构成的第二开关，用于基于第二控制来控制输入到电流镜像电路的电流。 另一个操作，推动操作或拉动操作由电流镜电路的电流输出执行。

公开(公告)号：US20050231493A1

公开(公告)日：2005-10-20

申请号：US11071190

申请日：2005-03-04

申请人： Satoshi Takahashi ,  Ryogo Yanagisawa ,  Toru Iwata

发明人： Satoshi Takahashi ,  Ryogo Yanagisawa ,  Toru Iwata

IPC分类号： G09G5/00 ,  G06F13/14 ,  G09G3/20 ,  H03K5/19 ,  H03L7/00 ,  H04N5/14

CPC分类号： G09G5/006 ,  G09G3/2092

摘要： A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.

摘要翻译： 用于根据输入时钟信号处理输入视频数据的视频信号处理器包括：输入部分，用于改变视频数据的格式并输出结果数据; 逻辑部分，用于对从输入部分输出的数据进行解码并输出解码数据; 以及频率检测器，用于检测时钟信号具有高于给定频率的频率，并将检测结果作为检测信号输出。 当时钟信号的频率高于给定频率时，根据检测信号停止构成视频信号处理器的电路的至少一部分的操作。

公开(公告)号：US06633607B1

公开(公告)日：2003-10-14

申请号：US09249695

申请日：1999-02-12

申请人： Hironori Akamatsu ,  Toru Iwata ,  Hiroyuki Yamauchi

发明人： Hironori Akamatsu ,  Toru Iwata ,  Hiroyuki Yamauchi

IPC分类号： H03K904

CPC分类号： H03M9/00 ,  H04L25/49

摘要： A semiconductor device includes: a transmitting section; and a receiving section, wherein the transmitting section and the receiving section are connected to each other through a bus, the transmitting section includes an encoding section for encoding data including a plurality of bits to produce bit-position information which indicates a position of at least one bit selected from the plurality of bits included in the data, and an output section for outputting the bit-position information onto the bus, and the receiving section includes an input section for receiving the bit-position information from the bus, and a decoding section for decoding the bit-position information to produce the data.

摘要翻译： 一种半导体器件包括：发送部分; 以及接收部分，其中所述发送部分和所述接收部分通过总线相互连接，所述发送部分包括用于对包括多个比特的数据进行编码的编码部分，以产生指示至少的位置的比特位置信息 从包含在数据中的多个比特中选择一个比特，以及用于将比特位置信息输出到总线上的输出部分，并且接收部分包括用于从总线接收比特位置信息的输入部分和解码 用于解码位位置信息以产生数据。

公开(公告)号：US06542038B2

公开(公告)日：2003-04-01

申请号：US09986288

申请日：2001-11-08

申请人： Kazuko Nishimura ,  Toru Iwata

发明人： Kazuko Nishimura ,  Toru Iwata

IPC分类号： H03L700

CPC分类号： H03L7/087 ,  H03L7/081 ,  H03L7/0891 ,  H03L7/18

摘要： A phase-offset detecting phase comparator for comparing a reference signal and an auxiliary comparison signal which is a frequency-divided VCO output in terms of a phase to detect phase offset, and producing first and second delay control signals corresponding to the phase offset; a first delay element for adding delay to the auxiliary comparison signal by the first delay control signal to produce a comparison signal; a second delay element for adding delay to the VCO output by the second delay control signal to produce a PLL output; and a dummy frequency divider for adding delay corresponding to a frequency divider to the PLL output are provided.

摘要翻译： 相位偏移检测相位比较器，用于比较基准信号和辅助比较信号，所述辅助比较信号是相位相位的分频VCO输出以检测相位偏移，并产生对应于相位偏移的第一和第二延迟控制信号; 第一延迟元件，用于通过第一延迟控制信号将延迟添加到辅助比较信号，以产生比较信号; 第二延迟元件，用于通过第二延迟控制信号向VCO输出添加延迟以产生PLL输出; 并且提供用于将对应于分频器的延迟添加到PLL输出的虚拟分频器。

公开(公告)号：US06198415B1

公开(公告)日：2001-03-06

申请号：US09365882

申请日：1999-08-03

申请人： Takefumi Yoshikawa ,  Toru Iwata

发明人： Takefumi Yoshikawa ,  Toru Iwata

IPC分类号： H03M900

CPC分类号： H03M9/00

摘要： A control voltage is supplied from a phase locked loop (PLL), which includes a phase detector and a voltage controlled oscillator (VCO), to a delay circuit. The VCO is made up of a plurality of inverters connected together in a ring. The control voltage is also supplied to each of these inverters so as to control an oscillation frequency of the VCO. The control voltage is defined based on a phase difference between a reference clock signal and an oscillation clock signal. The delay circuit is made up of a plurality of inverters connected in series to each other. A delay caused by each of these inverters is controlled with the same voltage as the control voltage. A serial signal is input to an initial-stage one of the inverters. A latch circuit latches the output signals of the respective inverters of the delay circuit in response to a latch clock signal, which has been generated by dividing the frequency of the reference clock signal. And based on a result of latching, a parallel signal is output.

摘要翻译： 控制电压从包括相位检测器和压控振荡器（VCO）的锁相环（PLL）提供给延迟电路。 VCO由环形连接在一起的多个反相器构成。 控制电压也被提供给这些反相器中的每一个，以便控制VCO的振荡频率。 基于参考时钟信号和振荡时钟信号之间的相位差来定义控制电压。 延迟电路由彼此串联连接的多个反相器组成。 由这些逆变器中的每一个引起的延迟由与控制电压相同的电压来控制。 串行信号被输入到初级反相器之一。 锁存电路响应于通过划分参考时钟信号的频率产生的锁存时钟信号来锁存延迟电路的各个反相器的输出信号。 并且基于锁存的结果，输出并行信号。

公开(公告)号：US06191632B1

公开(公告)日：2001-02-20

申请号：US09359727

申请日：1999-07-23

申请人： Toru Iwata ,  Hironori Akamatsu

发明人： Toru Iwata ,  Hironori Akamatsu

IPC分类号： H03K300

CPC分类号： H03K5/153 ,  G06F1/10 ,  H03K5/133

摘要： A clock generation circuit comprises a clock wiring having opposed first and second ends, through which a clock is transmitted from the first end to the second end, and a plurality of clock phase adjustment circuits for generating internal clocks in accordance with the clock supplied from the clock wiring. Each of the clock phase adjustment circuits comprises a first-end side terminal and a second-end side terminal which are connected to a first-end side point and a second-end side point of the circuit, respectively, the points being positioned on both sides of a reference point of the clock wiring; a delay line for delaying a clock supplied from one of the terminals and outputting an internal clock; and a delay control circuit for performing feedback control on a delay of the clock in the delay means in accordance with the phase of the clock supplied from the other terminal so that the phase of the internal clock matches the phase of the clock at the reference point of the cock wiring. Therefore, regardless of the distances from the first end (clock input end) of the clock wiring to the respective clock phase adjustment circuits, internal clocks of the same phase are output from the clock phase adjustment circuits.

摘要翻译： 时钟发生电路包括具有相对的第一和第二端的时钟布线，通过该时钟布线从第一端发送到第二端，以及多个时钟相位调整电路，用于根据从第一端提供的时钟产生内部时钟 时钟接线。 每个时钟相位调整电路包括分别连接到电路的第一端侧点和第二端侧点的第一端侧端子和第二端侧端子，所述点位于两者上 侧面参考点的时钟布线; 用于延迟从一个终端提供的时钟并输出内部时钟的延迟线; 以及延迟控制电路，用于根据从另一个终端提供的时钟的相位对延迟装置中的时钟的延迟执行反馈控制，使得内部时钟的相位与参考点的时钟的相位匹配 的公鸡接线。 因此，不管从时钟线的第一端（时钟输入端）到各时钟相位调整电路的距离，从时钟相位调整电路输出同相的内部时钟。

公开(公告)号：US6140864A

公开(公告)日：2000-10-31

申请号：US927061

申请日：1997-09-10

申请人： Takashi Hirata ,  Toru Iwata ,  Hironori Akamatsu

发明人： Takashi Hirata ,  Toru Iwata ,  Hironori Akamatsu

IPC分类号： G06F1/26 ,  G05F3/02

CPC分类号： G06F1/26

摘要： In an LSI circuit, respective voltages on power-source lines connected to the respective sources of transistors which are turned OFF in a circuit block in the standby state are controlled by a power-source-voltage control circuit to vary in response to variations in the threshold voltages of the transistors. Consequently, the differential voltage (Vgs-Vt) between the gate-to-source voltage Vgs of each of the transistors and the threshold voltage Vt thereof is held constant at a given value, so that an OFF-state leakage current flowing through the transistor in the circuit block in the standby state is reduced and held constant at a given value. What results is a reduction in the power consumption of the circuit block in the standby state.

摘要翻译： 在LSI电路中，通过电源电压控制电路来控制在待机状态下在电路块中断开的与晶体管的各个源连接的电源线上的各个电压，以响应于 晶体管的阈值电压。 因此，每个晶体管的栅 - 源电压Vgs与其阈值电压Vt之间的差分电压（Vgs-Vt）保持恒定在给定值，使得流过晶体管的截止状态漏电流 处于待机状态的电路块减小并保持恒定在给定值。 在待机状态下电路块的功耗降低是什么结果。

公开(公告)号：US6137306A

公开(公告)日：2000-10-24

申请号：US345012

申请日：1999-07-02

申请人： Takashi Hirata ,  Toru Iwata

发明人： Takashi Hirata ,  Toru Iwata

IPC分类号： H03K19/0175 ,  H03K5/00 ,  H03K5/08 ,  H03K5/13 ,  H03K19/003 ,  H04L25/14 ,  H03K17/16

CPC分类号： H04L25/14 ,  H03K19/00323 ,  H03K5/08 ,  H03K5/13 ,  H03K2005/00058 ,  H03K2005/00156

摘要： An input buffer of the present invention includes: a plurality of receiver circuits for performing different phase adjustments on an input signal, and outputting the differently phase-adjusted signals; a pattern detection circuit for detecting a period of time for which a voltage of the input signal has remained unchanged; and a signal selection circuit for selecting one of the output signals received from the receiver circuits based on the detection result from the pattern detection circuit.

摘要翻译： 本发明的输入缓冲器包括：多个接收器电路，用于对输入信号执行不同的相位调整，并输出不同的相位调整信号; 用于检测输入信号的电压保持不变的时间段的模式检测电路; 以及信号选择电路，用于基于来自图案检测电路的检测结果来选择从接收器电路接收的输出信号之一。

公开(公告)号：US6009024A

公开(公告)日：1999-12-28

申请号：US46880

申请日：1998-03-24

申请人： Takashi Hirata ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Satoshi Takahashi ,  Yutaka Terada

发明人： Takashi Hirata ,  Hiroyuki Yamauchi ,  Hironori Akamatsu ,  Keiichi Kusumoto ,  Toru Iwata ,  Satoshi Takahashi ,  Yutaka Terada

IPC分类号： G11C7/06 ,  G11C7/00

CPC分类号： G11C7/06

摘要： A semiconductor memory of the present invention includes: a plurality of memory cells; a pair of local bit lines connected to the plurality of memory cells; a local sense amplifier for amplifying a potential difference between the pair of local bit lines; a pair of global bit lines electrically connected to the pair of local bit lines through a switch; and a global sense amplifier for amplifying a potential difference between the pair of global bit lines, wherein the local sense amplifier includes a plurality of transistors, each of the plurality of transistors included in the local sense amplifier is a transistor of a first conductivity type, and the global sense amplifier includes a transistor of a second conductivity type different from the first conductivity type.

摘要翻译： 本发明的半导体存储器包括：多个存储单元; 连接到所述多个存储器单元的一对局部位线; 本地读出放大器，用于放大一对局部位线之间的电位差; 一对全局位线通过开关电连接到该对局部位线; 以及用于放大所述一对全局位线之间的电位差的全局读出放大器，其中所述局部读出放大器包括多个晶体管，所述局部读出放大器中包括的所述多个晶体管中的每一个是第一导电类型的晶体管， 并且全球感测放大器包括不同于第一导电类型的第二导电类型的晶体管。