公开(公告)号：US07030688B2

公开(公告)日：2006-04-18

申请号：US10500875

申请日：2003-05-22

申请人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

发明人： Shiro Dosho ,  Naoshi Yanagisawa ,  Masaomi Toyama ,  Keijiro Umehara ,  Masahiro Fukui ,  Takefumi Yoshikawa ,  Toru Iwata ,  Shiro Sakiyama ,  Ryoichi Suzuki

IPC分类号： H03K5/00

CPC分类号： H03L7/0812 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/093

摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.

摘要翻译： 本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。 低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311） 电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

公开(公告)号：US07176708B2

公开(公告)日：2007-02-13

申请号：US10716615

申请日：2003-11-20

申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

IPC分类号： H03K19/007

CPC分类号： H04L25/493

摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

摘要翻译： 在通过电缆接收数据和时钟信号的接收机电路中，通过频率检测电路检测基于数据或时钟信号获得的信号的转变次数，并且当转换次数不大于预定的集合 输出用于复位包括在数据处理单元中的串行 - 并行转换器电路的操作的信号，以便控制接收数据的输出。 因此，在不提供上拉电阻器和下拉电阻器的情况下，可以以低功耗检测电缆的断开，并且可以提高抗噪声性能。

公开(公告)号：US07675314B2

公开(公告)日：2010-03-09

申请号：US12081154

申请日：2008-04-11

申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

IPC分类号： H03K19/007

CPC分类号： H04L25/493

摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

摘要翻译： 在通过电缆接收数据和时钟信号的接收机电路中，通过频率检测电路检测基于数据或时钟信号获得的信号的转变次数，并且当转换次数不大于预定的集合 输出用于复位包括在数据处理单元中的串行 - 并行转换器电路的操作的信号，以便控制接收数据的输出。 因此，在不提供上拉电阻器和下拉电阻器的情况下，可以以低功耗检测电缆的断开，并且可以提高抗噪声性能。

公开(公告)号：US20090262876A1

公开(公告)日：2009-10-22

申请号：US12090774

申请日：2006-03-10

申请人： Yukio Arima ,  Toru Iwata ,  Makoto Miyake ,  Takefumi Yoshikawa

发明人： Yukio Arima ,  Toru Iwata ,  Makoto Miyake ,  Takefumi Yoshikawa

IPC分类号： H04L7/00

CPC分类号： H04L7/033 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/0891

摘要： A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the process of determining whether a data edge lies within the window are performed in parallel to each other, and the phase comparison result is output only if the data edge lies within the window. With this configuration, it is possible to perform an accurate phase comparison process with no errors without requiring high-precision delay circuits.

摘要翻译： 用于高速数据通信的定时恢复过程中的相位比较处理定义数据窗口并将窗口中的时钟的相位与数据边缘的相位进行比较，以实现并行处理，其中相位比较和 执行数据边缘位于窗口内的处理是彼此并行执行的，并且仅当数据边缘位于窗口内时才输出相位比较结果。 利用这种配置，可以在不需要高精度延迟电路的情况下，无误地执行精确的相位比较处理。

公开(公告)号：US07397268B2

公开(公告)日：2008-07-08

申请号：US11653340

申请日：2007-01-16

申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

IPC分类号： H03K19/007

CPC分类号： H04L25/493

摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

公开(公告)号：US20070115025A1

公开(公告)日：2007-05-24

申请号：US11653340

申请日：2007-01-16

申请人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

发明人： Tsuyoshi Ebuchi ,  Toru Iwata ,  Takefumi Yoshikawa

IPC分类号： H03K19/007

CPC分类号： H04L25/493

摘要： In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.

公开(公告)号：US20070041483A1

公开(公告)日：2007-02-22

申请号：US11586587

申请日：2006-10-26

申请人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

发明人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

IPC分类号： H03D3/24

CPC分类号： H04L25/45 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0891 ,  H04L7/033

摘要： A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

摘要翻译： 驱动器和接收器提供数据信号，其基于具有常规位模式的串行数据，例如时钟，其包括在调整周期期间彼此交替的1和0，并且基于具有任意的串行数据 在调整周期后的转移期间的位模式。 占空因数控制器调节驱动器或接收器的数据转换特性，使得从接收器提供的数据信号的占空比在调整周期中等于50％，并且具有被调整的数据转换特性。 时钟恢复单元恢复与在传送时段中从接收器提供的数据信号同步的时钟，并且基于来自数据信号的经调整的转换特性。

公开(公告)号：US07136441B2

公开(公告)日：2006-11-14

申请号：US10038613

申请日：2002-01-08

申请人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

发明人： Toru Iwata ,  Hiroyuki Yamauchi ,  Takefumi Yoshikawa

IPC分类号： H04L7/00

CPC分类号： H04L25/45 ,  H03L7/0807 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0891 ,  H04L7/033

摘要： A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

公开(公告)号：US06198415B1

公开(公告)日：2001-03-06

申请号：US09365882

申请日：1999-08-03

申请人： Takefumi Yoshikawa ,  Toru Iwata

发明人： Takefumi Yoshikawa ,  Toru Iwata

IPC分类号： H03M900

CPC分类号： H03M9/00

摘要： A control voltage is supplied from a phase locked loop (PLL), which includes a phase detector and a voltage controlled oscillator (VCO), to a delay circuit. The VCO is made up of a plurality of inverters connected together in a ring. The control voltage is also supplied to each of these inverters so as to control an oscillation frequency of the VCO. The control voltage is defined based on a phase difference between a reference clock signal and an oscillation clock signal. The delay circuit is made up of a plurality of inverters connected in series to each other. A delay caused by each of these inverters is controlled with the same voltage as the control voltage. A serial signal is input to an initial-stage one of the inverters. A latch circuit latches the output signals of the respective inverters of the delay circuit in response to a latch clock signal, which has been generated by dividing the frequency of the reference clock signal. And based on a result of latching, a parallel signal is output.

摘要翻译： 控制电压从包括相位检测器和压控振荡器（VCO）的锁相环（PLL）提供给延迟电路。 VCO由环形连接在一起的多个反相器构成。 控制电压也被提供给这些反相器中的每一个，以便控制VCO的振荡频率。 基于参考时钟信号和振荡时钟信号之间的相位差来定义控制电压。 延迟电路由彼此串联连接的多个反相器组成。 由这些逆变器中的每一个引起的延迟由与控制电压相同的电压来控制。 串行信号被输入到初级反相器之一。 锁存电路响应于通过划分参考时钟信号的频率产生的锁存时钟信号来锁存延迟电路的各个反相器的输出信号。 并且基于锁存的结果，输出并行信号。

公开(公告)号：US06323756B1

公开(公告)日：2001-11-27

申请号：US09486868

申请日：2000-05-26

申请人： Takefumi Yoshikawa ,  Toru Iwata ,  Hiroyuki Yamauchi

发明人： Takefumi Yoshikawa ,  Toru Iwata ,  Hiroyuki Yamauchi

IPC分类号： H04M1104

CPC分类号： H03K19/017545 ,  H03K19/0013

摘要： The data transmission device 1a of the present invention includes a driver 10 for sending data, a receiver 20 for receiving the data sent from the driver 10, a transmission line path 30 for connecting between the driver 10 and the receiver 20, and a variable impedance element 40 having a controllably variable impedance. The variable impedance element 40 is connected to the transmission line path 30. The data transmission line device 1a can reduce power consumption and occurrence of skew.

摘要翻译： 本发明的数据传输装置1a包括用于发送数据的驱动器10，用于接收从驱动器10发送的数据的接收器20，用于连接驱动器10和接收器20的传输线路径30和可变阻抗 元件40具有可控制的可变阻抗。 可变阻抗元件40连接到传输线路径30.数据传输线设备1a可以降低功耗并产生偏斜。