公开(公告)号：US20220004217A1

公开(公告)日：2022-01-06

申请号：US17480803

申请日：2021-09-21

Applicant: STMICROELECTRONICS (ALPS) SAS

Inventor： Kuno Lenz

IPC: G05F3/26 ,  G05F1/56

Abstract: In an embodiment, a device for generating a first current from a second current, comprises: an output transistor configured to generate the first current; a first circuit configured to generate a third current representative of the second current and to draw it from a first node; a second circuit configured to generate a fourth current representative of the first current and to supply it to the first node; and a third circuit receiving a fifth current representative of a difference between the third and fourth currents, the third circuit being configured to generate a sixth current representative of the fifth current and to draw it from a control terminal of the output transistor.

公开(公告)号：US11115061B2

公开(公告)日：2021-09-07

申请号：US17010351

申请日：2020-09-02

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Fabrice Romain ,  Mathieu Lisart ,  Patrick Arnould

IPC: H03M13/29 ,  G06F11/10

Abstract: A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.

公开(公告)号：US20210240862A1

公开(公告)日：2021-08-05

申请号：US17161194

申请日：2021-01-28

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Gilles PELISSIER ,  Nicolas ANQUET ,  Delphine LE-GOASCOZ

IPC: G06F21/72 ,  H04L9/08 ,  H04L9/32 ,  H04L9/06

Abstract: An integrated circuit includes a secure hardware environment having a first input that receives a key number. A key generation device generates a secret key from the key number and a unique key. A signature generation device generates a signature associated with the key number. A second input of the secure hardware environment receives encrypted binary data. A decryption device operates to decrypt the received encrypted binary data using the secret key. A third input the secure hardware environment receives an authentication signature. An authentication device authorizes use of the secret key to decrypt only if the signature generated by the signature generation device is identical to the authentication signature.

公开(公告)号：US20210234362A1

公开(公告)日：2021-07-29

申请号：US17157555

申请日：2021-01-25

Applicant: STMicroelectronics (Alps) SAS

Inventor： Michel Bouche

IPC: H02H3/20 ,  H02H3/02 ,  H02H3/033

Abstract: An embodiment of the present disclosure relates to an electronic circuit including a first switch coupling a first node of the circuit to an input/output terminal of the circuit; a second switch coupling the first node to a second node of application of a fixed potential; and a high-pass filter having an input coupled to the terminal and an output coupled to a control terminal of the second switch.

公开(公告)号：US11070754B1

公开(公告)日：2021-07-20

申请号：US16828423

申请日：2020-03-24

Applicant: STMicroelectronics Asia Pacific Pte Ltd. ,  STMicroelectronics (Alps) SAS

Inventor： Hongliang Zhang ,  Lookah Chua ,  Celine Mas ,  Wai Yin Hnin

IPC: H04N5/225 ,  H04N5/359 ,  H04N5/374

Abstract: In an embodiment, an image sensor includes: first and second voltage rails; first and second regulators configured to generate first and second regulated voltage at the first and second voltage rails, respectively; and a plurality of pixels coupled to the first and second voltage rails. Each pixel includes: first and second transistor coupled first and second storage capacitor, respectively. A third transistor is coupled between a control terminal of the first transistor and the first or second voltage rails. The third transistor is configured to limit a slew rate of current flowing between the control terminal of the second transistor and the first or second voltage rails to a first slew rate when the image sensor operates in global shutter mode, and to a second slew rate when the image sensor operates in rolling mode, the first slew rate being smaller than the second slew rate.

公开(公告)号：US20210157668A1

公开(公告)日：2021-05-27

申请号：US16953993

申请日：2020-11-20

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grand Ouest) SAS

Inventor： Loic Pallardy ,  Nicolas Anquet ,  Dragos Davidescu

IPC: G06F11/07 ,  G06F13/42 ,  G06F21/44

Abstract: In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.

公开(公告)号：US20200336138A1

公开(公告)日：2020-10-22

申请号：US16849020

申请日：2020-04-15

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Alps) SAS

Inventor： Giovanni Luca TORRISI ,  Domenico aka Massimo PORTO ,  Christophe ROUSSEL

IPC: H03K17/00 ,  H02P7/03

Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.

公开(公告)号：US20200081776A1

公开(公告)日：2020-03-12

申请号：US16562025

申请日：2019-09-05

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Gerald BRIAT ,  Antoine DE-MUYNCK ,  Alessandro BASTONI ,  Stephane MARMEY

IPC: G06F11/10 ,  G11C17/00

Abstract: An error-correction code memory includes memory locations for storing data. The memory is programmed to store one or more intentionally invalid words. Testing of an error correction circuit for the memory is performed by accessing the one or more intentionally invalid words and performing an error detection and error correction operation.

公开(公告)号：US10534389B2

公开(公告)日：2020-01-14

申请号：US16130706

申请日：2018-09-13

Applicant: STMicroelectronics (Alps) SAS

Inventor： Kuno Lenz

IPC: G05F1/575 ,  H02M3/156 ,  H02M3/158

Abstract: In some embodiments, a Miller compensation and stabilization device for a feedback control loop includes a capacitor and a control circuit. The capacitor has a first terminal configured to be coupled to an output of a comparator of the feedback control loop and a second terminal. The control circuit is coupled to the second terminal of the capacitor and is configured to control, in response to a voltage applied to a setpoint input of the feedback control loop, a first voltage across the first and second terminals of the capacitor by controlling a value of a potential of the second terminal of the capacitor such that the first voltage is lower than a threshold.

公开(公告)号：US10514749B2

公开(公告)日：2019-12-24

申请号：US15467614

申请日：2017-03-23

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics SA

Inventor： Vincent Huard ,  Silvia Brini ,  Chittoor Parthasarathy

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G06F11/30 ,  G06F11/32 ,  G06F15/78 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296

Abstract: A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.