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    Circuitry and methods minimizing output switching noise through split-level signaling and bus division enabled by a third power supply
    134.
    发明授权
    Circuitry and methods minimizing output switching noise through split-level signaling and bus division enabled by a third power supply 有权
    电路和方法通过由第三电源使能的分级信号和总线划分来最小化输出开关噪声

    公开(公告)号：US09245598B2

    公开(公告)日：2016-01-26

    申请号：US14188468

    申请日：2014-02-24

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis

    IPC: H03K19/003 ,  G11C7/02 ,  G11C7/10 ,  G11C11/4074

    CPC classification number: G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/4074 ,  H03K19/00353

    Abstract: Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals.

    Abstract translation: 这里公开了用于使用高共模和低共模信令在并行总线上传输数据的电路和方法。 发射器级配置为工作在三种可能的电源电压中的两种：高Vddq电压，低Vssq电压和中间Vx电压。 在一个实施例中，将奇数编号的输出驱动到总线的奇数发送器级使用Vddq和Vx电源，使得奇数输出包括高共模信号。 将偶数编号的输出驱动到总线的偶数发送器级使用Vx和Vssq电源，使得偶数输出包括低共模信号。

    TIME-DOMAIN SIGNAL GENERATION
    135.
    发明申请
    TIME-DOMAIN SIGNAL GENERATION 有权
    时域信号产生

    公开(公告)号：US20150261902A1

    公开(公告)日：2015-09-17

    申请号：US14724554

    申请日：2015-05-28

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis

    IPC: G06F17/50

    CPC classification number: G06F17/5036

    Abstract: Methods and apparatuses disclose various embodiments of time-domain signal generation. In one embodiment a method includes receiving an input waveform having a plurality of cycles with aspects of the input waveform being input and controllable by an end-user. A set of transform coefficients is calculated for at least some of the cycles using at least one hardware-based processor. A time-domain cycle is calculated for each set of transform coefficients. Other methods and apparatuses are disclosed.

    Abstract translation: 方法和装置公开了时域信号产生的各种实施例。 在一个实施例中，一种方法包括接收具有多个周期的输入波形，其中输入波形的方面由最终用户输入和控制。 使用至少一个基于硬件的处理器针对至少一些周期来计算一组变换系数。 为每组变换系数计算时域周期。 公开了其他方法和装置。

    Adaptive on die decoupling devices and methods
    136.
    发明授权
    Adaptive on die decoupling devices and methods 有权
    适用于芯片去耦器件和方法

    公开(公告)号：US09077305B2

    公开(公告)日：2015-07-07

    申请号：US14153580

    申请日：2014-01-13

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis ,  Steven Bodily

    IPC: H03H7/00 ,  H03H7/01 ,  H01L23/64 ,  H01L49/02

    CPC classification number: H03H7/0138 ,  H01L23/642 ,  H01L28/20 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Semiconductor dies and methods are described, such as those including a first capacitive pathway having a first effective series resistance (ESR) and a second capacitive pathway having an adjustable ESR. One such device provides for optimizing the semiconductor die for different operating conditions such as operating frequency. As a result, semiconductor dies can be manufactured in a single configuration for several different operating frequencies, and each die can be tuned to reduce (e.g. minimize) supply noise, such as by varying the ESR or the capacitance of at least one of the pathways.

    Abstract translation: 描述了半导体管芯和方法，例如包括具有第一有效串联电阻（ESR）的第一电容通路和具有可调节ESR的第二电容通路的那些。 一种这样的器件提供用于在诸如工作频率的不同操作条件下优化半导体管芯。 结果，可以以单个配置制造半导体管芯用于几个不同的工作频率，并且可以调整每个管芯以减小（例如最小化）电源噪声，例如通过改变至少一个通路的ESR或电容 。

    REFERENCE VOLTAGE GENERATOR FOR SINGLE-ENDED COMMUNICATION SYSTEMS
    137.
    发明申请
    REFERENCE VOLTAGE GENERATOR FOR SINGLE-ENDED COMMUNICATION SYSTEMS 有权
    单端通信系统参考电压发生器

    公开(公告)号：US20150070052A1

    公开(公告)日：2015-03-12

    申请号：US14543004

    申请日：2014-11-17

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis

    IPC: H03K5/24

    CPC classification number: H03K5/2472 ,  G06F13/00 ,  G06F13/4072 ,  G11C5/14 ,  H04B1/16 ,  H04L25/06

    Abstract: An improved reference voltage (Vref) generator for a single-ended receiver in a communication system is disclosed. The Vref generator in one example comprises a cascoded current source for providing a current, I, to a resistor, Rb, to produce the Vref voltage (I*Rb). Because the current source isolates Vref from a first of two power supplies, Vref will vary only with the second power supply coupled to Rb. As such, the improved Vref generator is useful in systems employing signaling referenced to that second supply but having decoupled first supplies. For example, in a communication system in which the second supply (E.g. Vssq) is common to both devices, but the first supply (Vddq) is not, the disclosed Vref generator produces a value for Vref that tracks Vssq but not the first supply. This improves the sensing of Vssq-referenced signals in such a system.

    Abstract translation: 公开了用于通信系统中的单端接收机的改进的参考电压（Vref）发生器。 一个示例中的Vref发生器包括用于向电阻器Rb提供电流I以产生Vref电压（I * Rb）的级联电流源。 因为电流源将Vref与两个电源中的第一个隔离，所以Vref将仅随耦合到Rb的第二个电源而变化。 因此，改进的Vref发生器在使用参考该第二电源但具有解耦第一电源的信令的系统中是有用的。 例如，在其中第二电源（例如Vssq）对于两个装置是公共的但是第一电源（Vddq）不是）的通信系统中，所公开的Vref发生器产生用于跟踪Vssq而不是第一电源的Vref的值。 这改善了在这种系统中对Vssq参考信号的感测。

    DATA BUS INVERSION APPARATUS, SYSTEMS, AND METHODS
    138.
    发明申请
    DATA BUS INVERSION APPARATUS, SYSTEMS, AND METHODS 有权
    数据总线反相装置，系统和方法

    公开(公告)号：US20140313062A1

    公开(公告)日：2014-10-23

    申请号：US14320127

    申请日：2014-06-30

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Timothy M. Hollis

    IPC: H03M5/00 ,  G11C7/10

    CPC classification number: H03M5/00 ,  G06F13/4234 ,  G11C7/02 ,  G11C7/1006 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Apparatus, systems, and methods are disclosed such as those that operate to encode data bits transmitted on a plurality of channels according to at least one of multiple Data Bus Inversion (DBI) algorithms. Additional apparatus, systems, and methods are disclosed.

    Abstract translation: 公开了装置，系统和方法，例如根据多个数据总线反转（DBI）算法中的至少一个，对在多个信道上发送的数据位进行编码的装置，系统和方法。 公开了附加装置，系统和方法。

    CIRCUITRY AND METHODS MINIMIZING OUTPUT SWITCHING NOISE THROUGH SPLIT-LEVEL SIGNALING AND BUS DIVISION ENABLED BY A THIRD POWER SUPPLY
    139.
    发明申请
    CIRCUITRY AND METHODS MINIMIZING OUTPUT SWITCHING NOISE THROUGH SPLIT-LEVEL SIGNALING AND BUS DIVISION ENABLED BY A THIRD POWER SUPPLY 有权
    电路和方法通过第三次电源启用的分离电平信号和总线部分最小化输出开关噪声

    公开(公告)号：US20140169116A1

    公开(公告)日：2014-06-19

    申请号：US14188468

    申请日：2014-02-24

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis

    IPC: G11C7/02 ,  G11C11/4074

    CPC classification number: G11C7/02 ,  G11C7/1051 ,  G11C7/1057 ,  G11C11/4074 ,  H03K19/00353

    Abstract: Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals.

    Abstract translation: 这里公开了用于使用高共模和低共模信令在并行总线上传输数据的电路和方法。 发射器级配置为工作在三种可能的电源电压中的两种：高Vddq电压，低Vssq电压和中间Vx电压。 在一个实施例中，将奇数编号的输出驱动到总线的奇数发送器级使用Vddq和Vx电源，使得奇数输出包括高共模信号。 将偶数编号的输出驱动到总线的偶数发送器级使用Vx和Vssq电源，使得偶数输出包括低共模信号。

    Multi-level signaling in memory with wide system interface
    140.
    发明授权
    Multi-level signaling in memory with wide system interface 有权

    公开(公告)号：US12237953B2

    公开(公告)日：2025-02-25

    申请号：US17564867

    申请日：2021-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Timothy M. Hollis ,  Markus Balb ,  Ralf Ebert

    IPC: H04L25/49 ,  G11C7/10

    Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

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