LINK EVALUATION FOR A MEMORY DEVICE
    2.
    发明公开

    公开(公告)号:US20230197181A1

    公开(公告)日:2023-06-22

    申请号:US18112830

    申请日:2023-02-22

    CPC classification number: G11C29/44 G11C29/38 G11C29/12005 G11C2207/2254

    Abstract: Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

    Interrupt signaling for a memory device

    公开(公告)号:US12099746B2

    公开(公告)日:2024-09-24

    申请号:US17116180

    申请日:2020-12-09

    CPC classification number: G06F3/0659 G06F3/0619 G06F3/0679

    Abstract: Methods, systems, and devices for interrupt signaling for a memory device are described. A memory device may transmit an interrupt signal to a host device to alter a sequence of operations that would otherwise be executed by the host device. The memory device may transmit the interrupt signal in response to detecting an error condition at the memory device, a performance degradation at the memory device, or another trigger event. In some examples, the memory device may include a dedicated interrupt pin for transmitting interrupt signals. Alternatively, the memory device may transmit interrupt signals via a pin also sued to transmit error detection codes. For example, the memory device may transmit an interrupt signal before or after an error detection code or may invert the error detection code to indicate the interrupt, in which case the inverted error detection code may act as an interrupt signal.

    Link evaluation for a memory device

    公开(公告)号:US11615862B2

    公开(公告)日:2023-03-28

    申请号:US17121314

    申请日:2020-12-14

    Abstract: Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

    Detection of illegal commands
    5.
    发明授权

    公开(公告)号:US11354064B2

    公开(公告)日:2022-06-07

    申请号:US16719891

    申请日:2019-12-18

    Abstract: Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.

    DETECTION OF ILLEGAL COMMANDS
    6.
    发明申请

    公开(公告)号:US20200210110A1

    公开(公告)日:2020-07-02

    申请号:US16719891

    申请日:2019-12-18

    Abstract: Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.

    Multi-level signaling in memory with wide system interface

    公开(公告)号:US10425260B2

    公开(公告)日:2019-09-24

    申请号:US15854600

    申请日:2017-12-26

    Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

    DETECTION OF ILLEGAL COMMANDS
    8.
    发明申请

    公开(公告)号:US20220365727A1

    公开(公告)日:2022-11-17

    申请号:US17826994

    申请日:2022-05-27

    Abstract: Methods, systems, and devices for detection of illegal commands are described. A memory device, such as a dynamic random access memory (DRAM), may receive a command from a device, such as a host device, to perform an access operation on at least one memory cell of a memory device. The memory device may determine, using a detection component, that a timing threshold associated with an operation of the memory device would be violated by performing the access operation. The memory device may refrain from executing the access operation based on determining that performing the access operation included in the command would violate the timing threshold. The memory device may transmit, to the device, an indication that performing the command would violate the timing threshold.

    MEMORY HEALTH STATUS REPORTING
    9.
    发明申请

    公开(公告)号:US20210182141A1

    公开(公告)日:2021-06-17

    申请号:US17118455

    申请日:2020-12-10

    Abstract: Methods, systems, and devices for memory health status reporting are described. A memory device may output to a host device a parameter value, which may be indicative of metric or condition related to the performance or reliability (e.g., a health status) of the memory device of the memory device. The host device may thereby determine that the memory device is degraded, possibly prior to device or system failure. Based on the parameter value, the host device may take preventative action, such as quarantining the memory device, deactivating the memory device, or swapping the memory device for another memory device.

    MULTI-LEVEL SIGNALING IN MEMORY WITH WIDE SYSTEM INTERFACE

    公开(公告)号:US20200028720A1

    公开(公告)日:2020-01-23

    申请号:US16536179

    申请日:2019-08-08

    Abstract: Techniques are provided herein to increase a rate of data transfer across a large number of channels in a memory device using multi-level signaling. Such multi-level signaling may be configured to increase a data transfer rate without increasing the frequency of data transfer and/or a transmit power of the communicated data. An example of multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the multi-level signal may be configured to represent a plurality of bits of data.

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