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公开(公告)号：US11594272B2
公开(公告)日：2023-02-28
申请号：US17409608
申请日：2021-08-23
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Adam S. El-Mansouri , Suryanarayana B. Tatapudi , John D. Porter
IPC: G11C11/22
Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.
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公开(公告)号：US20190333562A1
公开(公告)日：2019-10-31
申请号：US15962938
申请日：2018-04-25
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Adam S. El-Mansouri , Suryanarayana B. Tatapudi , John D. Porter
IPC: G11C11/22
Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.
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公开(公告)号：US20180005671A1
公开(公告)日：2018-01-04
申请号：US15703365
申请日：2017-09-13
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Timothy M. Hollis , Huy T. Vo , Dirgha Khatri
CPC classification number: G11C7/10 , G11C5/04 , G11C7/1006 , G11C7/22
Abstract: Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the memory module and to provide DBI data and a corresponding DBI bit to a respective memory of the plurality of memories.
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公开(公告)号：US20150171849A1
公开(公告)日：2015-06-18
申请号：US14109341
申请日：2013-12-17
Applicant: Micron Technology, Inc.
IPC: H03K5/151
CPC classification number: G06F1/06 , G06F1/08 , G06F1/324 , G06F1/3275 , H03K5/1515 , Y02D10/126 , Y02D10/14
Abstract: Apparatuses and methods for providing clock signals are described herein. An example apparatus may include a clock generator circuit. The clock generator circuit may be configured to selectively provide first and second intermediate signals to a multiplexer in a clock path to provide an output clock signal with a first frequency when operating in a first mode and to selectively provide the first and second intermediate clock signals to the multiplexer in the clock path to provide the output clock signal with a second frequency when operating in a second mode.
Abstract translation: 本文描述了用于提供时钟信号的装置和方法。 示例性装置可以包括时钟发生器电路。 时钟发生器电路可以被配置为在时钟路径中选择性地向多路复用器提供第一和第二中间信号，以在第一模式下操作时提供具有第一频率的输出时钟信号，并且选择性地将第一和第二中间时钟信号提供给 时钟路径中的多路复用器，以在第二模式下操作时提供具有第二频率的输出时钟信号。
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公开(公告)号：US20220020416A1
公开(公告)日：2022-01-20
申请号：US17387301
申请日：2021-07-28
Applicant: Micron Technology, Inc.
Inventor： Hyun Yoo Lee , Suryanarayana B. Tatapudi , Huy T. Vo , Ferdinando Bedeschi , Umberto Di Vincenzo , Riccardo Muzzetto
IPC: G11C11/22 , G11C11/4094 , G11C11/4091
Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.
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Patent Agency Ranking
公开(公告)号：US11127449B2
公开(公告)日：2021-09-21
申请号：US15962938
申请日：2018-04-25
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Adam S. El-Mansouri , Suryanarayana B. Tatapudi , John D. Porter
IPC: G11C11/22
Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.
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公开(公告)号：US10667621B2
公开(公告)日：2020-06-02
申请号：US15957742
申请日：2018-04-19
Applicant: Micron Technology, Inc.
Inventor： Huy T. Vo , Adam S. El-Mansouri
Abstract: Methods and devices for reading a memory cell using multi-stage memory sensing are described. The memory cell may be coupled to a digit line after the digit line during a read operation. A transistor may be activated to couple an amplifier capacitor with the digit line during the read operation. The transistor may be deactivated for a portion of the read operation to isolate the amplifier capacitor from the digit line while the memory cell is coupled to the digit line. The transistor may be reactivated to recouple the amplifier capacitor to the digit line to help determine the value of the memory cell.
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公开(公告)号：US10600472B2
公开(公告)日：2020-03-24
申请号：US16105889
申请日：2018-08-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Scott J. Derner , Huy T. Vo , Patrick Mullarkey , Jeffrey P. Wright , Michael A. Shore
IPC: G11C11/4091 , G11C11/406 , G11C11/4072 , G11C11/4094 , G11C11/4096
Abstract: Systems and methods are provided for implementing an array reset mode. An example system includes at least one mode register configured to enable an array reset mode, a memory cell array including one or more sense amplifiers, and control logic. Each of the one or more sense amplifier may include at least a first terminal coupled to a first bit line and a second terminal coupled to a second bit line. The control logic may be coupled to the memory cell array, and in communication with the at least one mode register. The control logic may be configured to drive, in response to array reset mode being enabled, each of the first and second terminals of the sense amplifier to a bit-line precharge voltage that corresponds to a bit value to be written to respective memory cells associated with each of the first and second bit lines.
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公开(公告)号：US20200075076A1
公开(公告)日：2020-03-05
申请号：US16121224
申请日：2018-09-04
Applicant: Micron Technology, Inc.
Inventor： Hyun Yoo Lee , Suryanarayana B. Tatapudi , Huy T. Vo , Ferdinando Bedeschi , Umberto Di Vincenzo , Riccardo Muzzetto
IPC: G11C11/22 , G11C11/4091 , G11C11/4094
Abstract: Methods, systems, and devices for a source follower-based sensing architecture and sensing scheme are described. In one example, a memory device may include a sense circuit that includes two source followers that are coupled to each other and to a sense amplifier. A method of operating the memory device may include transferring a digit line voltage to one of the source followers and transferring a reference voltage to the other source follower. After transferring the digit line voltage and the reference voltage, the source followers may be enabled so that signals representative of the digit line voltage and the reference voltage are transferred from the outputs of the source followers to the sense amplifier for sensing.
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公开(公告)号：US20170337951A1
公开(公告)日：2017-11-23
申请号：US15159728
申请日：2016-05-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Timothy M. Hollis , Huy T. Vo , Dirgha Khatri
CPC classification number: G11C7/10 , G11C5/04 , G11C7/1006 , G11C7/22
Abstract: Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the memory module and to provide DBI data and a corresponding DBI bit to a respective memory of the plurality of memories.
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