公开(公告)号：US20240249758A1

公开(公告)日：2024-07-25

申请号：US18623355

申请日：2024-04-01

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L. Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/12

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US10943628B2

公开(公告)日：2021-03-09

申请号：US16518767

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Randon K. Richards ,  Dirgha Khatri

IPC: G11C7/22 ,  G11C8/18 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4093

Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

公开(公告)号：US20210027816A1

公开(公告)日：2021-01-28

申请号：US16518767

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Randon K. Richards ,  Dirgha Khatri

IPC: G11C7/22 ,  G06F13/16 ,  G11C8/18

Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

公开(公告)号：US09922686B2

公开(公告)日：2018-03-20

申请号：US15159728

申请日：2016-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Huy T. Vo ,  Dirgha Khatri

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/10 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/22

Abstract: Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the memory module and to provide DBI data and a corresponding DBI bit to a respective memory of the plurality of memories.

公开(公告)号：US20210383849A1

公开(公告)日：2021-12-09

申请号：US17244942

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L. Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C8/12 ,  G11C8/06 ,  G11C7/10

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US20210193203A1

公开(公告)日：2021-06-24

申请号：US17193955

申请日：2021-03-05

Applicant: Micron Technology, Inc.

Inventor： Randon K. Richards ,  Dirgha Khatri

IPC: G11C7/22 ,  G11C8/18 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4093

Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

公开(公告)号：US20180005671A1

公开(公告)日：2018-01-04

申请号：US15703365

申请日：2017-09-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Timothy M. Hollis ,  Huy T. Vo ,  Dirgha Khatri

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/10 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/22

Abstract: Apparatuses, memory modules, and methods for performing intra-module data bus inversion operations are described. An example apparatus include a memory module comprising a data bus inversion (DBI) and buffer circuit and a plurality of memories. The DBI and buffer circuit configured to encode a block of data received by the memory module and to provide DBI data and a corresponding DBI bit to a respective memory of the plurality of memories.

公开(公告)号：US11948661B2

公开(公告)日：2024-04-02

申请号：US17244942

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/12

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

公开(公告)号：US11830578B2

公开(公告)日：2023-11-28

申请号：US17992651

申请日：2022-11-22

Applicant: Micron Technology, Inc.

Inventor： Randon K. Richards ,  Dirgha Khatri

IPC: G11C7/22 ,  G11C8/18 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093

Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

公开(公告)号：US20230090116A1

公开(公告)日：2023-03-23

申请号：US17992651

申请日：2022-11-22

Applicant: Micron Technology, Inc.

Inventor： Randon K. Richards ,  Dirgha Khatri

IPC: G11C7/22 ,  G11C8/18 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4093

Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.