公开(公告)号：US20150076514A1

公开(公告)日：2015-03-19

申请号：US14027758

申请日：2013-09-16

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US08962430B2

公开(公告)日：2015-02-24

申请号：US13907237

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Qing Liu ,  Nicolas Loubet ,  Bruce Doris

IPC: H01L21/336 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/66477 ,  H01L21/76232 ,  H01L21/76283 ,  H01L29/0649

Abstract: On a substrate formed of a first semiconductor layer, an insulating layer and a second semiconductor layer, a silicon oxide pad layer and a silicon nitride pad layer are deposited and patterned to define a mask. The mask is used to open a trench through the first semiconductor layer and insulating layer and into the second semiconductor layer. A dual liner of silicon dioxide and silicon nitride is conformally deposited within the trench. The trench is filled with silicon dioxide. A hydrofluoric acid etch removes the silicon nitride pad layer along with a portion of the conformal silicon nitride liner. A hot phosphoric acid etch removes the silicon oxide pad layer, a portion of the silicon oxide filling the trench and a portion of the conformal silicon nitride liner. The dual liner protects against substrate etch through at an edge of the trench between the first and second semiconductor layers.

Abstract translation: 在由第一半导体层，绝缘层和第二半导体层形成的衬底上，沉积氧化硅衬垫层和氮化硅衬垫层以形成掩模。 掩模用于打开通过第一半导体层和绝缘层并进入第二半导体层的沟槽。 二氧化硅和氮化硅的双衬垫共形沉积在沟槽内。 沟槽填充有二氧化硅。 氢氟酸蚀刻将氮化硅衬垫层与一部分共形氮化硅衬垫一起去除。 热磷酸蚀刻去除氧化硅衬垫层，填充沟槽的氧化硅的一部分和保形氮化硅衬垫的一部分。 双衬垫在第一和第二半导体层之间的沟槽的边缘处防止衬底蚀刻。

公开(公告)号：US20150041898A1

公开(公告)日：2015-02-12

申请号：US13964009

申请日：2013-08-09

Applicant: GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Jin Cho

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for forming fully insulated finFETs beginning with a bulk semiconductor substrate are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first epitaxial layer may be sacrificial. A final gate structure may be formed around the fin structures, and the first epitaxial layer removed to form a void between a fin and the substrate. The void may be filled with an insulator to fully insulate the fin.

Abstract translation: 描述了以体半导体衬底开始形成完全绝缘的finFET的方法和结构。 用于finFET的鳍结构可以形成在生长在块状衬底上的两个外延层中。 第一外延层可以是牺牲的。 可以在翅片结构周围形成最终的栅极结构，并且去除第一外延层以在翅片和衬底之间形成空隙。 空隙可以填充绝缘体以使翅片完全绝缘。

公开(公告)号：US20150008521A1

公开(公告)日：2015-01-08

申请号：US14494979

申请日：2014-09-24

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L29/78 ,  H01L21/266 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06

CPC classification number: H01L29/7848 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/7849

Abstract: A transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

Abstract translation: 晶体管包括主体和构造成对身体的一部分施加应力的半导体区域。 例如，施加晶体管的沟道可以增加沟道中载流子的迁移率，从而可以降低晶体管的“导通”电阻。 例如，可以掺杂PFET的衬底，源极/漏极区域或者衬底和源/漏极区域，以对沟道进行压缩应力，从而增加沟道中空穴的迁移率。 或者，可以掺杂NFET的衬底，源极/漏极区域或衬底和源极/漏极区域两者以使通道拉伸应力，以增加沟道中电子的迁移率。

公开(公告)号：US20140353753A1

公开(公告)日：2014-12-04

申请号：US13906677

申请日：2013-05-31

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Balasubramanian Pranatharthiharan

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/7848 ,  H01L29/785

Abstract: Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET.

Abstract translation: 改进的鳍状场效应晶体管（FinFET）器件及其制造方法。 一方面，一种用于制造FinFET器件的方法包括：提供生长有硅外延层的硅衬底。 衬底上的牺牲结构由外延层形成。 在牺牲结构和暴露的衬底部分之上形成覆盖硅层，所述覆盖硅层具有均匀厚度的上部和下部，并且中间部分插入在不均匀厚度的上部和下部之间并且具有形成角度。 半导体散热片阵列由覆盖硅层和覆盖层上形成的非共形层形成。 去除牺牲结构，并且在通道区域下填充隔离结构的所得空隙。 在FinFET的鳍合并期间，在源极/漏极区域中形成源极和漏极。

公开(公告)号：US08900978B1

公开(公告)日：2014-12-02

申请号：US13905534

申请日：2013-05-30

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Douglas LaTulipe ,  Alexander Reznicek

IPC: H01L21/205 ,  H01L21/306 ,  H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/823425 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/4958 ,  H01L29/66628 ,  H01L29/66636

Abstract: A method for making a semiconductor device includes forming at least one gate stack on a layer comprising a first semiconductor material and etching source and drain recesses adjacent the at least one gate stack. The method further includes shaping the source and drain recesses to have a vertical side extending upwardly from a bottom to an inclined extension adjacent the at least one gate stack.

Abstract translation: 制造半导体器件的方法包括在包括第一半导体材料的层上形成至少一个栅极堆叠，以及邻近所述至少一个栅极堆叠的蚀刻源极和漏极凹陷。 该方法进一步包括成形源极和漏极凹槽以具有从底部向上延伸到与所述至少一个栅极堆叠相邻的倾斜延伸部的垂直侧。

公开(公告)号：US20140099773A1

公开(公告)日：2014-04-10

申请号：US14096515

申请日：2013-12-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS, INC.

Inventor： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

IPC: H01L21/768 ,  H01L21/762

CPC classification number: H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

公开(公告)号：US11569384B2

公开(公告)日：2023-01-31

申请号：US17074121

申请日：2020-10-19

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/15 ,  H01L29/16 ,  H01L29/161

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US10854606B2

公开(公告)日：2020-12-01

申请号：US16697103

申请日：2019-11-26

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.

公开(公告)号：US10515965B2

公开(公告)日：2019-12-24

申请号：US16035441

申请日：2018-07-13

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.