摘要:
An astable multivibrator operating in a current mode comprising two transistors with resistive cross-coupling between each collector and the other base and capacitive cross-coupling between emitters. The natural frequency of the multivibrator is determined by the emitter resistors and the cross-coupling capacitance, which is preferably adjustable. A crystal having a parallel resonant overtone mode at the desired frequency of operation of the oscillator is connected between the bases of the transistors. The cross-coupling capacitance is adjusted so that the natural frequency of the multivibrator is slightly higher than the resonant frequency of the crystal.
摘要:
A ferromagnetic plated wire memory having a nonaxially aligned easy direction of magnetization with respect to the longitudinal axis of the wire memory and having spaced apart sections of ferromagnetic material along the wire memory free of said easy direction of magnetization.
摘要:
The disclosure embodies a V-shaped sheet stack hopper having a downwardly directed opening at its apex. At the apex of the hopper, and in part forming one of the walls thereof, is a shiftable or positionable restricting member which forms a card restricting outlet with a resilient tire of a card feed roller. Mounted on the hopper and supporting the positionable restricting member is a body on which there is an adjustment member operable to establish a set restriction with the tire, corresponding to a given card thickness. Also mounted on the body is a shifter member by means of which the positionable member may be readily shifted to change the restriction to one for accommodating cards of other thickness.
摘要:
A TRANSLATOR OF ADDRESSES FOR A ROTATING RECORD MEMBER FILE. A PARAMETER CIRCUIT IS PROVIDED FOR EACH DIFFERENT INFORMATION FORMAT FOR WHICH ADDRESSES ARE TO BE TRANSLATED. EACH PARAMETER CIRCUIT FORMS CODED PARAMETER SIGNALS FOR THE CORRESPONDING FORMAT. AT LEAST ONE PARAMETER SIGNAL IS FORMED FOR EACH ADDRESS PART IN THE TRANSLATED ADDRESS. A CIRCUIT FORMS THE COMPLEMENT OF THE SIGNALS. AN ADDER RECEIVES THE ADDRESS TO BE TRANSLATED AND COMBINES THE ADDRESS WITH THE PARAMETER SIGNALS OR THE COMPLEMENT OF THE PARAMETER SIGNALS, THEREBY FORMING A CODED RESULT SIGNAL. THE ADDER ALSO COMBINES THE RESULTS FORMED THEREBY WITH THE PARAMETER SIGNALS OR THE COMPLEMENT OF THE PARAMETER SIGNALS. A COUNTER IS PROVIDED FOR EACH OF A PLURALITY OF THE ADDRESS PARTS AND COUNTS THE NUMBER OF TIMES THE CORRESPONDING PARAMETER COMPLEMENT IS COMBINED WITH THE ADDRESS OR THE RESULT SIGNALS BEFORE THE CODED RESULT SIGNALS BECOME LESS THAN ZERO. THE STATE OF THE COUNTERS AND THE RESULT AFTER ALL PARAMETER SIGNALS HAVE BEEN COMBINED, REPRESENT THE TRANSDUCER SELECTION AND ANGULAR POSITION PARTS OF THE TRANSLATED ADDRESS.
摘要:
A METHOD FOR ESTABLISHING A DIRECT BRANCH COMMUNICATION FROM AN OBJECT PROGRAM TO A SUBROUTINE OF THE MASTER CONTROL PROGRAM INCLUDES ADDRESS WORDS IDENTIFYING TER CONTROL PROGRAM INCLUDES ADDRESS WORDS IDENTIFYING THE LOCATIONS IN MEMORY OF THE SUBROUTINES TO WHICH A DIRECT BRANCH COMMUNICATION IS DESIRED. EACH ADDRESS WORD INCLUDES A UNIQUE FLAG DIGIT. WHEN AN OBJECT PROGRAM ATTEMPTS TO ESTABLISH A BRANCH COMMUNICATION TO A SUBROUTINE IN THE MASTER CONTROL PROGRAM BY FETCHING ONE OF THE ADDRESS WORDS, THE COMMUNICATION IS IN FACT ONLY ESTABLISHED IF THE FETCHED WORD CONTAINS THE FLAG DIGIT. THE SAME STEPS INITIATE THE EXECUTION OF A TEST ROUTINE EITHER IN THE EVENT THE INFORMATION CALLED BY THE OBJECT PROGRAM DOES NOT CONTAIN THE FLAG DIGIT OR IN THE EVENT A HARDWARE INTERRUPTION TAKES PLACE. APPARATUS FOR ESTABLISHING THE DIRECT BRANCH COMMUNICATION INCLUDES A FIRST REGISTER FOR STORING COMPUTER INSTRUCTIONS, A SECOND REGISTER FOR STORING A MEMORY ADDRESS, AND A THIRD REGISTER FOR STORING INFORMATION TO BE EXCHANGED WITH THE LOCATION IN THE COMPUTER MEMORY IDENTIFIED BY THE ADDRESS STORED IN THE SECOND REGISTER. RESPONSIVE TO THE STORAGE OF A BRANCH COMMUNICATION INSTRUCTION IN THE FIRST REGISTER, A GATE TRANSFERS A SELECTED ADDRESS WORD IDENTIFYING THE LOCATION IN THE MEMORY OF A SUBROUTINE FROM THE MEMORY TO THE THIRD REGISTER. A CHECK CIRCUIT INSPECTS THE SELECTED ADDRESS WORD TO DETERMINE IF A FLAG DIGIT IS PRESENT. RESPONSIVE TO THE PRESENCE OF THE FLAG DIGIT, A GATE TRANSFERS THE SELECTED ADDRESS WORD TO THE SECOND REGISTER TO INITIATE EXECUTION OF THE CORRESPONDING SUBROUTINE.
摘要:
THE PRESENT APPLICATION DISCLOSES AN INTERRUPT SYSTEM CAPABLE OF USE IN A FULLY MODULAR DATA PROCESSING SYSTEM. IT PROVIDES APPARATUS MEANS FOR ENABLING NOT ONLY RECORDATION AND IMMEDIATE RESPONSIVE RECOGNITION OF A COMPREHENSIVE SET OF INTERRUPT CONDITIONS BUT ALSO FOR RECORDATION WITHOUT IMMEDIATE RESPONSIVE RECOGNITION OF SUCH CONDITIONS. IN ADDITION, IT PROVIDES AN INTERRUPT SYSTEM WHICH IS OPERATIVE IN ITS INTERRUPTED OR CONTROL MODE TO EXECUTE
OBJECT PROGRAMS WHICH HERETOFORE COULD BE EXECUTED ONLY IN ITS NORMAL MODE OF OPERATION. IT ALSO DISCLOSES AN INTERRUPT SYSTEM HAVING IMPROVED EXTERNAL INTERRUPT CAPABILITIES ESPECIALLY IN THE MODULE FAIL AREA.
摘要:
AN ARTICLE HOLDER FOR SUPPORTING ARTICLES WHILE BEING SUBJECTED TO ELECTRODEPOSITING ACTION, SUCH AS ELECTROPLATING, WHICH IS COMPOSED OF A RELATIVELY THICK PAD OR SHEET OF RESILIENTLY COMPRESSIBLE, ELECTRICALLY INSULATING MATERIAL HAVING EMBEDDED THEREIN ONE OR MORE WOVEN WIRE MESH SCREEN BEING IN PLANES PARALLEL TO AND SPACED APART FROM ONE ANOTHER AND TO THE OPPOSITE SURFACES OF THE SHEET. FOR RETAINING THE ARTICLES IN PLACE DURING DURING THIS OPERATION, THE INSULATING SHEET IS DRILLED OR OTHERWISE SHAPED TO PROVIDE HOLES EACH OPENING OUT ON AT LEAST ONE SURFACE OF THE SHEET AND EXTENDING THROUGH THE EMBEDDED WIRE SCREENS SO THAT SEVERED WIRES ARE EXPOSED IN THE HOLES. ARTICLES TO BE SUBJECTED TO ELECTRODEPOSITING ACTION ARE SHAPED WITH A PART THEREOF WHICH IS SNUGLY RECEIVED IN A HOLE AND HELD OR RETAINED IN THIS MANNER ON THE HOLDER WHLE OTHER EXPOSED AREAS OF THE ARTICLE RECEIVE THE ELECTRODEPOSITED COATING. THE INSERTED PART OF EACH SUCH ARTICLE IS ENGAGED BY THE EXPOSED SEVERED WIRES OF THE SCREENS TO FORM AN ELECTRICAL CONNECTION THEREWITH. PROVISION IS MADE FOR ELECTRICALLY CONNECTING EACH SUCH EMBEDDED WIRE SCREEN TO AN EXTERNAL SOURCE OF ELECTRICAL ENERGY.
摘要:
1,242,989. Data processing. BURROUGHS CORP. 30 Sept., 1968 [2 Oct., 1967], No. 4513/71. Divided out of 1,233,925. Heading G4A. In data processing apparatus, mark words in stack storage areas link such areas together by each containing a value which references another mark word, a mark word not containing the value being stored in a stack area currently in use, a reference word in the stack area currently in use having a value referencing a mark word for the stack area containing a programme word which refers to a new procedure, there being means for combining this value with the mark word for the stack area currently in use to provide a link therein to the stack area containing the programme word. The disclosure is as in the parent.
摘要:
1,233,926. Data processing. BURROUGHS CORP. 30 Sept., 1968 [2 Oct., 1967], No. 46291/68. Heading G4A. A data processing system has a memory containing a plurality of first-in, last-out stacks of information and can access a desired word using a stack base address and an increment. A core memory can store a control table, a data descriptor array, a segment dictionary, and last-in-first-out job stacks. Transistor flip-flop display registers D0, D1, D2, D3 ... point to (contain the absolute address of) MSCW mark words in some of these stored entities as shown in Figs. 2, 4. Referring to Fig. 2, assuming job no. 3 is being processed, registers S, BOSR point to the top and bottom respectively of job stack no. 3. If a "load value" operator is read from memory for execution, the IRWS word at the top of job stack no. 3 is retrieved. If a (job) stack number in it specifies the same stack, i.e. in this case is equal to 3, DISP and 8 fields from the IRWS are added to the contents of BOSR to address memory to obtain a parameter which is loaded on to the top of the current job stack viz. stack no. 3. If the stack number in the IRWS specified a different stack, the contents of display register D0 (pointing to the base of the control table) are incremented by 2 to retrieve a DD from the control table which contains an ADDRESS field pointing to the base of the data descriptor array. The stack number specified in the IRWS is added to the ADDRESS field to retrieve a DD from the data descriptor array, an ADDRESS field of which points to the base of the required stack. This ADDRESS field is added to the DISP and 8 fields from the IRWS to retrieve the parameter which is loaded on to the top of the current job stack, viz. stack no. 3. An IRW word could have been used instead of an IRWS word in which case it would select a display register and provide a field #, the latter being added to the contents of the display register to address memory and obtain the parameter which is loaded on to the stack as before. Referring to Fig. 4 and assuming job no. 2 is being processed and an "enter" operator is read from memory, the IRW shown in job stack no. 2 is retrieved. The IRW selects a display register and provides a 8 field which is added to the display register contents to address memory to retrieve the PCW shown in job stack no. 2 (this PCW relating to procedure C which is to be "entered"). Fields of the PCW are inserted into registers in the computer for use during execution of procedure C. The PCW also selects the display register D1 (which points to the base of the segment dictionary) and provides an increment value which is added to its contents to retrieve an SD from the segment dictionary. An ADDRESS field in this SD points to (the starting address of) the required procedure C which can now be executed. An IRWS might have been used instead of the IRW in which case DISP and # fields in it are added to the contents of the BOSR to retrieve the PCW which is then used as before. The SD also specifies the length of the procedure. The entities pointed to by SD and DD words may be in peripheral disc storage rather than the core memory, this being indicated by a field in the SD or DD. If so, the entity is moved into core memory when required. The PCW also specifies the address of the first operator, and the machine state required. Thus procedures can be shared between jobs. Separate computers may work in parallel on the jobs. Parts of job stacks may be shared between jobs. The hardware facilitates handling of ALGOL or PL/I programmes.