公开(公告)号：US20200176420A1

公开(公告)日：2020-06-04

申请号：US16558304

申请日：2019-09-02

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/46 ,  H01L25/00

Abstract: A 3D semiconductor device, the device including: a first level; a second level; and a third level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed directly above the first level and includes a first plurality of arrays of memory cells, where the third level is disposed directly above the second level and includes a plurality of RF circuits, and where a portion of interconnections between the plurality of logic circuits includes the RF circuits.

公开(公告)号：US10388863B2

公开(公告)日：2019-08-20

申请号：US15452615

申请日：2017-03-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L27/108 ,  H01L21/762 ,  H01L27/06 ,  H01L27/11578 ,  H01L27/24 ,  H01L45/00

Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and is controlled by a third control line, where the second transistor is overlaying the first transistor and is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and third control line, and where the first transistor, the second transistor and the third transistor are all aligned to each other with less than 100 nm misalignment.

公开(公告)号：US10325651B2

公开(公告)日：2019-06-18

申请号：US15494525

申请日：2017-04-23

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: G11C13/00 ,  H01L27/24 ,  G11C29/00 ,  H01L45/00 ,  G11C11/404 ,  G11C11/4097 ,  H01L29/78 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11578 ,  H01L49/02 ,  G11C11/412 ,  G11C16/04

Abstract: A semiconductor device including: a first memory cell including a first transistor; and a second memory cell including a second transistor, where the second transistor overlays the first transistor and the second transistor is self-aligned to the first transistor, where access to the first memory cell is controlled by at least one junction-less transistor, and where the junction-less transistor is not part of the first memory cell and the second memory cell.

公开(公告)号：US20190164834A1

公开(公告)日：2019-05-30

申请号：US16246412

申请日：2019-01-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L21/8238 ,  H03K19/177 ,  G11C16/04 ,  H01L27/105 ,  H01L29/78 ,  G11C17/14 ,  H01L21/683 ,  H01L27/108 ,  H01L23/525 ,  H01L21/84 ,  H03K17/687 ,  H01L25/18 ,  H01L25/065 ,  H01L27/11 ,  H01L27/112 ,  H01L27/118 ,  G11C17/06 ,  H01L27/06 ,  H03K19/0948 ,  H01L29/786 ,  H01L27/092 ,  H01L23/36 ,  G11C29/00 ,  H01L21/762 ,  H01L27/02 ,  H01L23/544

Abstract: A method for producing a 3D memory device, the method including: providing a first level including a single crystal layer; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells includes one first transistor, where each of the second memory cells includes one second transistor, where at least one of the first or second transistors has a channel, a source and a drain having the same doping type, and where the forming at least one third level includes forming a window within the third level so to allow a lithography alignment through the third level to an alignment mark disposed underneath the third level.

公开(公告)号：US10297586B2

公开(公告)日：2019-05-21

申请号：US15990626

申请日：2018-05-26

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/02 ,  H01L25/00 ,  H01L21/304 ,  H01L25/18 ,  H01L21/78 ,  H01L21/762

Abstract: A method for processing a 3D semiconductor device, the method including: providing a wafer including a plurality of first dies, the plurality of first dies including a first transistor layer and a first interconnection layer; completing a step of transferring a plurality of second dies each overlaying at least one of the first dies, where each of the plurality of second dies includes a second transistor layer, where at least one of the plurality of first dies is substantially larger in area than at least one of the plurality of second dies, and where each of the plurality of second dies has a thickness greater than six microns; and completing a step of thinning the plurality of second dies, where each of the plurality of second dies has a thickness of less than 2 microns.

公开(公告)号：US10297580B2

公开(公告)日：2019-05-21

申请号：US15990684

申请日：2018-05-28

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L27/06 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L21/74 ,  H01L23/36 ,  H01L21/768 ,  H01L23/485 ,  H01L25/065

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a plurality of third transistors overlaying the second transistors; a third metal layer overlaying the plurality of third transistors; and a connective metal path between the third metal layer and at least one of the first transistors, where at least one of the plurality of third transistors is aligned to at least one of the plurality of first transistors with less than 40 nm alignment error, where the first metal layer is powered by a first voltage and the second metal layer is powered by a second voltage.

公开(公告)号：US20190067110A1

公开(公告)日：2019-02-28

申请号：US16171036

申请日：2018-10-25

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H01L21/8238

Abstract: A 3D semiconductor device including: a first level with first single crystal transistors; contact plugs; a first metal layer, where a portion of the contact plugs provide connections from the first transistors to the first metal, where connections formed logic circuits; a second level with second transistors; a third level with third transistors, where the second level overlays the first level, and where the third level overlays the second level; a second metal layer overlaying the third level, second level includes first memory cells where each of the memory cells include at least one of the second transistors; and vertically oriented conductive plugs, where the second transistors are aligned to the first transistors with less than 100 nm alignment error, where the second transistors are junction-less transistors, where one end of each of the vertically oriented conductive plugs are connected to the second metal layer, where at least one of the vertically oriented conductive plugs is disposed directly on one of the contact plugs.

公开(公告)号：US20190013213A1

公开(公告)日：2019-01-10

申请号：US16113860

申请日：2018-08-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/48 ,  H01L23/34 ,  H01L23/498 ,  H01L27/098 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L25/065 ,  H01L23/60 ,  H01L23/522

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming, at least in part a plurality of logic gates; a plurality of second transistors overlaying, at least in part the first single crystal layer; a plurality of third transistors overlaying, at least in part the second transistors; a second metal layer overlaying, at least in part the third transistors; Input/Output pads to provide connection to external devices, a local power grid to distribute power to the plurality of logic gates, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Serializer/Deserializer (“SerDes”) structure connected to at least one of the Input/Output pads, where a memory cell includes at least one of the third transistors.

公开(公告)号：US20190006240A1

公开(公告)日：2019-01-03

申请号：US16101438

申请日：2018-08-11

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L21/822 ,  H03K19/177 ,  H03K19/0948 ,  H03K17/687 ,  H01L29/786 ,  H01L29/78 ,  H01L27/118 ,  H01L27/112 ,  H01L27/11 ,  H01L27/108 ,  H01L27/105 ,  H01L27/092 ,  H01L27/06 ,  H01L27/02 ,  H01L25/18 ,  H01L25/065 ,  H01L23/544 ,  H01L23/525 ,  H01L23/36 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/683 ,  G11C29/00 ,  G11C17/14 ,  G11C17/06 ,  G11C16/04 ,  H01L23/48 ,  H01L23/00

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one first metal layer interconnecting the plurality of first transistors, where the interconnecting includes forming memory peripheral circuits; a plurality of second transistors underlying the first single crystal layer; a second metal layer overlaying the plurality of second transistors; a first memory cell underlying the memory peripheral circuits; a second memory cell underlying the first memory cell, and a non-volatile NAND memory, where the first memory cell includes at least one of the second transistors, where at least one of the second transistors includes a source, channel and drain, where the source, the channel and the drain have the same dopant type, here the non-volatile NAND memory includes the first memory cell, and where at least one of the second transistors includes a polysilicon channel.

公开(公告)号：US10115663B2

公开(公告)日：2018-10-30

申请号：US15913917

申请日：2018-03-06

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L23/498 ,  H01L23/34 ,  H01L27/098 ,  H01L27/092 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L25/065 ,  H01L23/60 ,  H01L23/522 ,  H01L23/367 ,  H01L25/00 ,  H01L23/373

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors and a first metal layer, where the first metal layer includes interconnecting the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; a plurality of third transistors overlaying the second transistors; a second metal layer overlaying the third transistors; and Input/Output pads to provide connection to external devices, where the third transistors are aligned to the first transistors with less than 40 nm misalignment, where the first single crystal layer includes an Electrostatic Discharge (“ESD”) structure connected to at least one of the Input/Output pads, where at least one of the third transistors is a junction-less transistor, and where a memory cell includes at least one of the third transistors.