公开(公告)号：US20100205415A1

公开(公告)日：2010-08-12

申请号：US12481499

申请日：2009-06-09

申请人： G. Glenn Henry ,  Terry Parks ,  Brent Bean

发明人： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC分类号： G06F9/38

CPC分类号： G06F9/30058 ,  G06F9/3867

摘要： A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, and a serializing instruction that updates the control value in the control register. The microprocessor completes all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction. Execution units update the control value in the control register in response to the serializing instruction. A fetch unit fetches, decodes, and unconditionally correctly resolves and retires the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.

摘要翻译： 微处理器包括控制寄存器，其存储影响微处理器的操作的控制值。 指令集架构包括基于存储在控制寄存器中的控制值来指定分支条件的条件转移指令，以及更新控制寄存器中的控制值的串行化指令。 微处理器通过串行化指令之前的指令完成对标志，寄存器和存储器的所有修改，并在串行化指令之前取出并执行下一条指令，将所有缓冲写入消耗到存储器中。 响应串行化指令，执行单元更新控制寄存器中的控制值。 取出单元基于存储在控制寄存器中的控制值来取得，解码和无条件地正确地解析和退出条件转移指令，而不是将条件转移指令分派到要解析的执行单元。

公开(公告)号：US20100205401A1

公开(公告)日：2010-08-12

申请号：US12481035

申请日：2009-06-09

申请人： G. Glenn Henry ,  Terry Parks ,  Brent Bean

发明人： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC分类号： G06F9/312 ,  G06F9/38

CPC分类号： G06F9/30058 ,  G06F9/3802 ,  G06F9/3867

摘要： A microprocessor includes a register that stores a state and a fetch unit that fetches instructions of a program. The program includes a first instruction followed non-immediately by a second instruction. The first instruction instructs the microprocessor to update the state in the register. The second instruction is a conditional branch instruction that specifies a branch condition based on the register state. The fetch unit dispatches the first instruction for execution but refrains from dispatching the second instruction for execution. Execution units receive the first instruction from the fetch unit and responsively update the register state. The fetch unit non-selectively correctly resolves the conditional branch instruction based on the register state when the execution units have updated the register state. The fetch unit also non-selectively refrains from sending the conditional branch instruction to the execution units to be resolved regardless of whether the execution units have updated the register state.

摘要翻译： 微处理器包括存储状态的寄存器和取得程序指令的读取单元。 该程序包括非紧接在第二条指令之后的第一条指令。 第一条指令指示微处理器更新寄存器中的状态。 第二条指令是指定基于寄存器状态的分支条件的条件分支指令。 提取单元调度第一条指令执行，但是不执行第二条指令执行。 执行单元从提取单元接收第一个指令，并响应更新寄存器状态。 当执行单元更新寄存器状态时，取出单元基于寄存器状态非选择性地正确地解析条件转移指令。 无论执行单元是否更新了寄存器状态，提取单元还非选择性地禁止将条件转移指令发送到待解析的执行单元。

公开(公告)号：US20090292931A1

公开(公告)日：2009-11-26

申请号：US12263199

申请日：2008-10-31

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F21/22 ,  G06F12/14

CPC分类号： G06F21/72 ,  G06F12/1408 ,  G06F21/12 ,  G06F21/14 ,  G06F21/554 ,  G06F21/70 ,  G06F21/71 ,  G06F21/73 ,  G06F21/74 ,  G06F21/82

摘要： An apparatus providing for a secure execution environment, including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has secure execution mode logic that is configured to provide for a secure execution mode within the microprocessor for execution of the secure application program. The secure execution mode logic records the state of the microprocessor in a non-volatile indicator register upon entry into the secure execution mode and upon exit from the secure execution mode. The secure non-volatile memory is coupled to the microprocessor via a private bus and is configured to store the secure application program. Transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.

摘要翻译： 一种提供安全执行环境的装置，包括微处理器和安全的非易失性存储器。 微处理器执行非安全应用程序和安全应用程序，其中通过系统总线从系统存储器访问非安全应用程序。 微处理器具有安全执行模式逻辑，其被配置为在微处理器内提供用于执行安全应用程序的安全执行模式。 安全执行模式逻辑在进入安全执行模式并退出安全执行模式时将微处理器的状态记录在非易失性指示符寄存器中。 安全非易失性存储器经由专用总线耦合到微处理器，并被配置为存储安全应用程序。 微处理器和安全非易失性存储器之间的专用总线上的交易与微处理器内的系统总线和对应的系统总线资源隔离。

公开(公告)号：US20090292894A1

公开(公告)日：2009-11-26

申请号：US12263143

申请日：2008-10-31

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F12/14 ,  G06F12/00

CPC分类号： G06F21/72 ,  G06F12/1408 ,  G06F21/12 ,  G06F21/14 ,  G06F21/554 ,  G06F21/70 ,  G06F21/71 ,  G06F21/73 ,  G06F21/74 ,  G06F21/75 ,  G06F21/82

摘要： An apparatus providing for a secure execution environment. The apparatus includes a microprocessor that is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The microprocessor has a non-secure memory and a secure volatile memory. The non-secure memory is configured to store portions of the non-secure application programs for execution by the microprocessor, where the non-secure memory is observable and accessible by the non-secure application programs and by system bus resources within the microprocessor. The secure volatile memory is configured to store the secure application program for execution by the microprocessor, where the secure volatile memory is isolated from the non-secure application programs and the system bus resources within the microprocessor.

摘要翻译： 一种提供安全执行环境的设备。 该装置包括被配置为执行非安全应用程序和安全应用程序的微处理器，其中通过系统总线从系统存储器访问非安全应用程序。 微处理器具有非安全存储器和安全易失性存储器。 非安全存储器被配置为存储用于由微处理器执行的非安全应用程序的部分，其中非安全存储器是可观察的并且可由非安全应用程序和微处理器内的系统总线资源访问。 安全易失性存储器被配置为存储用于由微处理器执行的安全应用程序，其中安全易失性存储器与非安全应用程序和微处理器内的系统总线资源隔离。

公开(公告)号：US20080256336A1

公开(公告)日：2008-10-16

申请号：US12034503

申请日：2008-02-20

申请人： G. Glenn Henry ,  Colin Eddy ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Colin Eddy ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/30 ,  G06F9/312

CPC分类号： G06F9/3824 ,  G06F9/26 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30123 ,  G06F9/30138 ,  G06F9/30174 ,  G06F9/3826

摘要： A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macroarchitecture, thereby enabling it to provide significantly more storage for microcode. The microinstruction set includes a microinstruction for loading data from the PRAM into the user-accessible registers, and a microinstruction for storing data from user-accessible registers to the PRAM. The microcode may also use the two microinstructions to load/store between the PRAM and non-user-accessible registers of the microarchitecture. Examples of PRAM uses include: computational temporary storage area; storage of x86 VMX VMCS in response to VMREAD and VMWRITE macroinstructions; instantiation of non-user-accessible storage, such as the x86 SMBASE register; and instantiation of x86 MSRs that tolerate the additional access latency of the PRAM, such as the IA32_SYSENTER_CS MSR.

摘要翻译： 微处理器包括专用RAM（PRAM），用于微码，这是非用户可访问的，并且在其自身与系统存储器地址空间不同的地址空间内。 PRAM比微处理器宏构架的用户可访问的寄存器更密集和更慢，从而使其能够为微码提供显着更多的存储。 微指令集包括用于将来自PRAM的数据加载到用户可访问寄存器中的微指令，以及用于将来自用户可访问寄存器的数据存储到PRAM的微指令。 微代码还可以使用两个微指令来加载/存储在微架构的PRAM和非用户可访问的寄存器之间。 PRAM使用的示例包括：计算临时存储区域; 存储x86 VMX VMCS以响应VMREAD和VMWRITE宏指令; 实例化非用户可访问的存储，如x86 SMBASE寄存器; 以及容忍PRAM的附加访问延迟（例如IA32_SYSENTER_CS MSR）的x86 MSR的实例化。

公开(公告)号：US07380103B2

公开(公告)日：2008-05-27

申请号：US10144589

申请日：2002-05-09

申请人： G. Glenn Henry ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/30 ,  G06F9/00

CPC分类号： G06F9/30185 ,  G06F9/3016 ,  G06F9/30174 ,  G06F9/30189

摘要： A microprocessor apparatus and method are provided, for selectively controlling write back of a result. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix precludes write back of the result, where the result is that which is produced by executing an operation prescribed by said extended instruction, and wherein the result would otherwise be written back into a destination register. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and executes the operation to generate the result, and precludes write back of the result.

摘要翻译： 提供了一种微处理器装置和方法，用于选择性地控制结果的回写。 该装置包括翻译逻辑和扩展执行逻辑。 翻译逻辑将扩展指令转换为相应的微指令。 扩展指令具有扩展前缀和扩展前缀标记。 扩展前缀排除结果的回写，其中结果是通过执行由所述扩展指令规定的操作产生的结果，并且其中结果将被写回目的地寄存器。 扩展前缀标记指示扩展前缀，其中扩展前缀标记是用于微处理器的指令集内的另外结构上指定的操作码。 扩展执行逻辑耦合到转换逻辑。 扩展执行逻辑接收相应的微指令，并执行产生结果的操作，并排除结果的回写。

公开(公告)号：US07334009B2

公开(公告)日：2008-02-19

申请号：US11428318

申请日：2006-06-30

申请人： G. Glenn Henry ,  Terry Parks

发明人： G. Glenn Henry ,  Terry Parks

IPC分类号： G06F7/58

CPC分类号： G06F7/58 ,  G06F9/30003 ,  G06F9/3004 ,  G06F9/30087 ,  G06F11/27

摘要： A microprocessor that includes a random number generator (RNG) and an instruction for storing random data bytes generated by the generator. The RNG includes multiple buffers for buffering the random bytes and counters associated with each buffer for keeping a count of the number of bytes in each buffer. The instruction specifies a destination for the bytes to be stored to. In one embodiment, the number of bytes written to memory is variable and is the number of bytes available when the instruction is executed; in another, the instruction specifies the number. If variable, the instruction atomically stores a count specifying the number of valid bytes actually stored. In one embodiment the destination is a location in system memory. The count may be stored to memory with the bytes; or the count may be stored to a user-visible register. An x86 REP prefix may be used.

摘要翻译： 包括随机数发生器（RNG）的微处理器和用于存储由发生器产生的随机数据字节的指令。 RNG包括用于缓冲与每个缓冲器相关联的随机字节和计数器的多个缓冲器，用于保持每个缓冲器中的字节数的计数。 该指令指定要存储的字节的目的地。 在一个实施例中，写入存储器的字节数是可变的，并且是执行指令时可用的字节数; 在另一个中，指令指定数字。 如果变量，则指令原子地存储一个指定实际存储的有效字节数的计数。 在一个实施例中，目的地是系统存储器中的位置。 计数可以用字节存储到存储器中; 或计数可以存储到用户可见的寄存器。 可以使用x86 REP前缀。

公开(公告)号：US07302551B2

公开(公告)日：2007-11-27

申请号：US10283397

申请日：2002-10-29

申请人： G. Glenn Henry ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/312 ,  G06F9/318

CPC分类号： G06F9/3812 ,  G06F9/30185 ,  G06F9/30189

摘要： An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruction. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies that store checking be suppressed for the extended instruction. The extended prefix tag is an otherwise architectural opcode within an existing instruction set. The fetch logic precludes store checking for pending store events associated with the extended instruction. The translation logic is coupled to the fetch logic. The translation logic translates the extended instruction into a micro instruction sequence that sequence directs the microprocessor to exclude store checking during execution of a prescribed operation.

摘要翻译： 提供了一种用于扩展微处理器指令集以允许在指令级别选择性地抑制存储检查的装置和方法。 该装置包括取指逻辑和翻译逻辑。 提取逻辑接收扩展指令。 扩展指令具有扩展前缀和扩展前缀标记。 扩展前缀指定对扩展指令禁止存储检查。 扩展前缀标记是现有指令集中的另一种体系结构操作码。 提取逻辑排除了与扩展指令相关联的待处理存储事件的存储检查。 翻译逻辑耦合到提取逻辑。 翻译逻辑将扩展指令转换成微指令序列，序列指示微处理器在执行规定的操作期间排除存储检查。

公开(公告)号：US07174355B2

公开(公告)日：2007-02-06

申请号：US10365601

申请日：2003-02-11

申请人： G. Glenn Henry ,  James R. Lundberg ,  Terry Parks

发明人： G. Glenn Henry ,  James R. Lundberg ,  Terry Parks

IPC分类号： G06F7/58

CPC分类号： G06F7/58 ,  G06F9/30003 ,  G06F9/3004 ,  G06F9/30087 ,  G06F11/27

摘要： A microprocessor with multiple random bit generators is disclosed. The multiple random bit generators each generate a stream of random bits. One of the streams of random bits is selected to be used to accumulate into random bytes for provision to application programs. Which of the multiple random bit generator random bit streams is selected is determined by a selection value stored in a control register of the microprocessor. The selection value is programmable by an instruction executed by the microprocessor.

摘要翻译： 公开了一种具有多个随机位发生器的微处理器。 多个随机比特发生器产生一个随机比特流。 选择随机比特流之一用于累加到随机字节中以供应给应用程序。 选择多个随机比特生成器随机比特流中的哪一个由存储在微处理器的控制寄存器中的选择值确定。 选择值由微处理器执行的指令编程。

公开(公告)号：US07058794B2

公开(公告)日：2006-06-06

申请号：US10279206

申请日：2002-10-22

申请人： Gerard M. Col ,  G. Glenn Henry ,  Terry Parks

发明人： Gerard M. Col ,  G. Glenn Henry ,  Terry Parks

IPC分类号： G06F9/00

CPC分类号： G06F9/30043 ,  G06F9/30101 ,  G06F9/3017

摘要： A method and apparatus are provided for storing a flags register in a processor. In response to a macro instruction directing the store operation, such as a push flags macro instruction, a mask is generated using privilege level information (i.e., current operating privilege level) to specify those bits of the flags register that can be stored. The mask is then ANDed with contents of the flags register to yield a result and the result is stored on a stack in memory.

摘要翻译： 提供了一种用于将标志寄存器存储在处理器中的方法和装置。 响应于指示存储操作的宏指令（诸如推式标志宏指令），使用特权级别信息（即当前操作特权级别）生成掩码，以指定可存储的标志寄存器的那些位。 然后将掩码与标志寄存器的内容进行AND运算，以产生结果，并将结果存储在内存中的堆栈中。