公开(公告)号：US09274795B2

公开(公告)日：2016-03-01

申请号：US13413258

申请日：2012-03-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC分类号： G06F9/30

CPC分类号： G06F9/30174 ,  G06F9/30076 ,  G06F9/30112 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/30196

摘要： A microprocessor processes conditional non-branch instructions that specify a condition and instruct the microprocessor to perform an operation if the condition is satisfied and otherwise to not perform the operation. A predictor provides a prediction about a conditional non-branch instruction. An instruction translator translates the conditional non-branch instruction into a no-operation microinstruction when the prediction predicts the condition will not be satisfied, and into a set of one or more microinstructions to unconditionally perform the operation when the prediction predicts the condition will be satisfied. An execution pipeline executes the no-operation microinstruction or the set of microinstructions. The predictor translates into a second set of one or more microinstructions to conditionally perform the operation when the prediction does not make a prediction. In the case of a misprediction, the translator re-translates the conditional non-branch instruction into the second set of microinstructions.

摘要翻译： 微处理器处理指定条件的条件非分支指令，并指示微处理器在条件满足的情况下执行操作，否则不执行操作。 预测器提供关于条件非分支指令的预测。 当预测预测条件不满足时，指令翻译器将条件非分支指令转换为无操作微指令，并且当预测预测条件将被满足时，指令转换为一组或多个微指令以无条件地执行操作 。 执行流水线执行无操作微指令或微指令集。 当预测不进行预测时，预测器转换成第二组一个或多个微指令以有条件地执行操作。 在错误预测的情况下，翻译者将条件非分支指令重新翻译成第二组微指令。

公开(公告)号：US09146742B2

公开(公告)日：2015-09-29

申请号：US13412914

申请日：2012-03-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC分类号： G06F9/48 ,  G06F9/50 ,  G06F9/54 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/30174 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3844 ,  G06F9/461

摘要： A microprocessor capable of operating as both an x86 ISA and an ARM ISA microprocessor includes first, second, and third storage that stores x86 ISA-specific, ARM ISA-specific, and non-ISA-specific state, respectively. When reset, the microprocessor initializes the first storage to default values specified by the x86 ISA, initializes the second storage to default values specified by the ARM ISA, initializes the third storage to predetermined values, and begins fetching instructions of a first ISA. The first ISA is the x86 ISA or the ARM ISA and a second ISA is the other ISA. The microprocessor updates the third storage in response to the first ISA instructions. In response to a subsequent one of the first ISA instructions that instructs the microprocessor to reset to the second ISA, the microprocessor refrains from modifying the non-ISA-specific state stored in the third storage and begins fetching instructions of the second ISA.

摘要翻译： 能够同时运行x86 ISA和ARM ISA微处理器的微处理器分别包含第一，第二和第三存储，它们分别存储特定于x86 ISA特定的ISA特定状态和非ISA特定状态。 当复位时，微处理器将第一个存储器初始化为由x86 ISA指定的默认值，将第二个存储初始化为由ARM ISA指定的默认值，将第三个存储初始化为预定值，并开始获取第一个ISA的指令。 第一个ISA是x86 ISA或ARM ISA，另一个ISA是另一个ISA。 微处理器响应于第一ISA指令更新第三存储器。 响应于指示微处理器重置到第二ISA的第一ISA指令中的随后的一个，微处理器不修改存储在第三存储器中的非ISA特定状态，并开始获取第二ISA的指令。

公开(公告)号：US09128701B2

公开(公告)日：2015-09-08

申请号：US13416879

申请日：2012-03-09

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30167 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30112 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3806

摘要： An ISA-defined instruction includes an immediate field having a first and second portions specifying first and second values, which instructs the microprocessor to perform an operation using a constant value as one of its source operands. The constant value is the first value rotated/shifted by a number of bits based on the second value. An instruction translator translates the instruction into one or more microinstructions. An execution pipeline executes the microinstructions generated by the instruction translator. The instruction translator, rather than the execution pipeline, generates the constant value for the execution pipeline as a source operand of at least one of the microinstructions for execution by the execution pipeline. Alternatively, if the immediate field value is not within a predetermined subset of values known by the instruction translator, the instruction translator generates, rather than the constant, a second microinstruction for execution by the execution pipeline to generate the constant.

摘要翻译： ISA定义的指令包括具有指定第一和第二值的第一和第二部分的立即字段，其指示微处理器使用常数值作为其源操作数之一执行操作。 常数值是基于第二值旋转/移位多个位的第一值。 指令翻译器将指令转换为一个或多个微指令。 执行流水线执行指令转换器生成的微指令。 指令转换器而不是执行流水线，将执行流水线的常量值作为执行流水线执行的至少一个微指令的源操作数。 或者，如果立即字段值不在指令转换器已知的值的预定子集内，则指令转换器生成第二微指令而不是常数，用于由执行流水线执行以产生常数。

公开(公告)号：US09032189B2

公开(公告)日：2015-05-12

申请号：US13333520

申请日：2011-12-21

申请人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30141 ,  G06F9/30174

摘要： A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.

摘要翻译： 一种微处理器，其执行结构指令，指示其在第一和第二源操作数上执行操作以产生结果，并且仅当其结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。 硬件指令转换器将指令转换为第一和第二微指令。 要执行第一个微指令，执行流水线对源操作数执行操作以生成结果。 要执行第二个微指令，如果架构条件标志满足条件，则将目标寄存器写入由第一微指令生成的结果，如果结构条件标志不满足条件标志，则将目标寄存器写入目标寄存器的当前值 条件。

公开(公告)号：US08930679B2

公开(公告)日：2015-01-06

申请号：US12604767

申请日：2009-10-23

申请人： Matthew Daniel Day ,  Rodney E. Hooker

发明人： Matthew Daniel Day ,  Rodney E. Hooker

IPC分类号： G06F9/34 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3838 ,  G06F9/3834 ,  G06F9/3861

摘要： An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a dependency that identifies an instruction upon which the store instruction depends for its data. A register alias table (RAT), coupled to the queue of entries, is configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order. In response to encountering a load instruction the RAT determines whether sources of the load instruction used to compute its load address match the sources of the store instruction in an entry of the queue, and if so, causes the load instruction to share the dependency of the matching store instruction.

摘要翻译： 一种无序执行微处理器，用于减少由于存储冲突而必须重播加载指令的可能性。 微处理器包括条目队列，每个条目被配置为保存识别用于计算其存储地址的存储指令的源的信息，并且保持识别存储指令对其数据所依赖的指令的依赖性。 耦合到条目队列的寄存器别名表（RAT）被配置为以程序顺序遇到指令，并且生成用于确定指令何时执行程序顺序的依赖关系。 响应于遇到加载指令，RAT确定用于计算其加载地址的加载指令的源是否与队列的条目中的存储指令的源匹配，如果是，则使加载指令共享 匹配商店指令。

公开(公告)号：US08924695B2

公开(公告)日：2014-12-30

申请号：US13333631

申请日：2011-12-21

申请人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/30072 ,  G06F9/30123 ,  G06F9/30174

摘要： An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition. To execute the first microinstruction, if the non-architectural indicator updated by the first microinstruction indicates the architectural condition flags satisfy the condition, it updates the destination register with the result; otherwise, it updates the destination register with the current value of the destination register.

摘要翻译： 架构指令指示微处理器对第一和第二源操作数执行操作以产生结果，并且只有在体系结构条件标志满足建筑指令中指定的条件时才将结果写入目的寄存器。 硬件指令翻译器将架构指令转换为第一和第二微指令。 为了执行第一微指令，执行流水线对源操作数执行操作以生成结果，确定架构条件标志是否满足条件，并更新非架构指示符以指示架构条件标志是否满足条件。 为了执行第一微指令，如果由第一微指令更新的非架构指示符指示架构条件标志满足条件，则用结果更新目的寄存器; 否则，它将使用目标寄存器的当前值更新目标寄存器。

公开(公告)号：US08880857B2

公开(公告)日：2014-11-04

申请号：US13333572

申请日：2011-12-21

申请人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Gerard M. Col ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/30

CPC分类号： G06F9/30189 ,  G06F9/30094 ,  G06F9/30174

摘要： A microprocessor includes a hardware instruction translator that translates an architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the shift operation on the first source operand to generate the first result and a carry flag value and updates a non-architectural carry flag with the generated carry flag value. To execute the second microinstruction, it performs the second operation on the first result and the second operand to generate the second result and new condition flag values based on the second result. If a architectural condition flags satisfy the condition, it updates the architectural carry flag with the non-architectural carry flag value and updates at least one of the other architectural condition flags with the corresponding generated new condition flag values; otherwise, it updates the architectural condition flags with the current value of the architectural condition flags.

摘要翻译： 微处理器包括将架构指令转换成第一和第二微指令的硬件指令转换器。 为了执行第一微指令，执行流水线对第一源操作数执行移位操作以产生第一结果和进位标志值，并且利用所生成的进位标志值更新非架构进位标志。 为了执行第二微指令，它对第一结果和第二操作数执行第二操作，以基于第二结果产生第二结果和新条件标志值。 如果架构条件标志满足条件，则使用非架构进位标志值来更新架构进位标志，并用对应的生成的新条件标志值来更新其他架构状态标志中的至少一个; 否则，它使用架构条件标志的当前值更新架构条件标志。

公开(公告)号：US08880851B2

公开(公告)日：2014-11-04

申请号：US13224310

申请日：2011-09-01

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC分类号： G06F9/30 ,  G06F9/26

CPC分类号： G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

摘要： A microprocessor includes a hardware instruction translator that translates x86 ISA and ARM ISA machine language program instructions into microinstructions, which are encoded in a distinct manner from the x86 and ARM instructions. An execution pipeline executes the microinstructions to generate x86/ARM-defined results. The microinstructions are distinct from the results generated by the execution of the microinstructions by the execution pipeline. The translator directly provides the microinstructions to the execution pipeline for execution. Each time the microprocessor performs one of the x86 ISA and ARM ISA instructions, the translator translates it into the microinstructions. An indicator indicates either x86 or ARM as a boot ISA. After reset, the microprocessor initializes its architectural state, fetches its first instructions from a reset address, and translates them all as defined by the boot ISA. An instruction cache caches the x86 and ARM instructions and provides them to the translator.

摘要翻译： 微处理器包括硬件指令转换器，将x86 ISA和ARM ISA机器语言程序指令转换为微指令，它们以不同于x86和ARM指令的方式进行编码。 执行流水线执行微指令以生成x86 / ARM定义的结果。 微指令与由执行管道执行微指令生成的结果不同。 翻译器直接向执行管道提供微指令以供执行。 每当微处理器执行x86 ISA和ARM ISA指令之一时，翻译器将其转换为微指令。 指示符指示x86或ARM作为引导ISA。 复位后，微处理器初始化其架构状态，从复位地址获取其第一条指令，并按照引导ISA定义将其全部转换。 指令缓存缓存x86和ARM指令，并将其提供给翻译器。

公开(公告)号：US08392666B2

公开(公告)日：2013-03-05

申请号：US12582591

申请日：2009-10-20

申请人： Rodney E. Hooker ,  Colin Eddy

发明人： Rodney E. Hooker ,  Colin Eddy

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F15/00 ,  G06F9/30 ,  G06F9/40 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC分类号： G06F12/0844

摘要： An apparatus detects a load-store collision within a microprocessor between a load operation and an older store operation each of which accesses data in the same cache line. Load and store byte masks specify which bytes contain the data specified by the load and store operation within a word of the cache line in which the load and data begins, respectively. Load and store word masks specify which words contain the data specified by the load and store operations within the cache line, respectively. Combinatorial logic uses the load and store byte masks to detect the load-store collision if the data specified by the load and store operations begin in the same cache line word, and uses the load and store word masks to detect the load-store collision if the data specified by the load and store operations do not begin in the same cache line word.

摘要翻译： 一种装置在加载操作和较旧的存储操作之间检测微处理器内的加载存储冲突，每个操作都访问同一高速缓存行中的数据。 加载和存储字节掩码分别指定哪些字节包含由加载和存储操作指定的数据，分别在加载和数据开始的高速缓存行的字中。 加载和存储字幕指定哪些字分别包含由缓存行中的加载和存储操作指定的数据。 组合逻辑使用加载和存储字节掩码来检测加载存储器冲突，如果由加载和存储操作指定的数据在相同的高速缓存行字中开始，并且使用加载和存储字掩码来检测加载存储器冲突，如果 由加载和存储操作指定的数据不会在同一个高速缓存行字中开始。

公开(公告)号：US20120272003A1

公开(公告)日：2012-10-25

申请号：US13535152

申请日：2012-06-27

申请人： Clinton Thomas Glover ,  Colin Eddy ,  Rodney E. Hooker ,  Albert J. Loper

发明人： Clinton Thomas Glover ,  Colin Eddy ,  Rodney E. Hooker ,  Albert J. Loper

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0859 ,  G06F12/0897 ,  G06F2212/6022

摘要： A microprocessor configured to access an external memory includes a first-level cache, a second-level cache, and a bus interface unit (BIU) configured to interface the first-level and second-level caches to a bus used to access the external memory. The BIU is configured to prioritize requests from the first-level cache above requests from the second-level cache. The second-level cache is configured to generate a first request to the BIU to fetch a cache line from the external memory. The second-level cache is also configured to detect that the first-level cache has subsequently generated a second request to the second-level cache for the same cache line. The second-level cache is also configured to request the BIU to refrain from performing a transaction on the bus to fulfill the first request if the BIU has not yet been granted ownership of the bus to fulfill the first request.

摘要翻译： 被配置为访问外部存储器的微处理器包括：第一级高速缓存，第二级高速缓存和总线接口单元（BIU），其被配置为将第一级和第二级高速缓存连接到用于访问外部存储器的总线 。 BIU被配置为优先考虑来自第二级缓存的来自第二级缓存的请求的请求。 第二级缓存被配置为生成对BIU的第一请求以从外部存储器获取高速缓存行。 第二级缓存还被配置为检测第一级高速缓存随后已经为同一高速缓存行生成了第二级缓存的第二请求。 第二级缓存还被配置为如果BIU尚未被授予总线的所有权以满足第一请求，则要求BIU避免在总线上执行事务以满足第一请求。