公开(公告)号：US20140122847A1

公开(公告)日：2014-05-01

申请号：US14007116

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/26

CPC分类号： G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

摘要： An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.

摘要翻译： 指令转换器接收指定条件，目标/数据寄存器，基址寄存器，偏移源和存储器寻址模式的条件加载/存储指令。 只有当条件标志满足条件时，指令才指示微处理器将数据从存储单元加载到目标寄存器（条件加载）中，或者将数据从数据寄存器（条件存储）​​存储到存储单元。 偏移源指定偏移量是立即值还是偏移量寄存器中的值。 寻址模式指定条件标志满足条件时是否更新基址寄存器。 指令翻译器将条件加载指令转换为多个微指令，其作为偏移源，寻址模式以及条件指令是条件加载还是存储指令的函数而变化。 无序执行流水线执行微指令以生成指令指定的结果。

公开(公告)号：US20080256336A1

公开(公告)日：2008-10-16

申请号：US12034503

申请日：2008-02-20

申请人： G. Glenn Henry ,  Colin Eddy ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Colin Eddy ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/30 ,  G06F9/312

CPC分类号： G06F9/3824 ,  G06F9/26 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30123 ,  G06F9/30138 ,  G06F9/30174 ,  G06F9/3826

摘要： A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macroarchitecture, thereby enabling it to provide significantly more storage for microcode. The microinstruction set includes a microinstruction for loading data from the PRAM into the user-accessible registers, and a microinstruction for storing data from user-accessible registers to the PRAM. The microcode may also use the two microinstructions to load/store between the PRAM and non-user-accessible registers of the microarchitecture. Examples of PRAM uses include: computational temporary storage area; storage of x86 VMX VMCS in response to VMREAD and VMWRITE macroinstructions; instantiation of non-user-accessible storage, such as the x86 SMBASE register; and instantiation of x86 MSRs that tolerate the additional access latency of the PRAM, such as the IA32_SYSENTER_CS MSR.

摘要翻译： 微处理器包括专用RAM（PRAM），用于微码，这是非用户可访问的，并且在其自身与系统存储器地址空间不同的地址空间内。 PRAM比微处理器宏构架的用户可访问的寄存器更密集和更慢，从而使其能够为微码提供显着更多的存储。 微指令集包括用于将来自PRAM的数据加载到用户可访问寄存器中的微指令，以及用于将来自用户可访问寄存器的数据存储到PRAM的微指令。 微代码还可以使用两个微指令来加载/存储在微架构的PRAM和非用户可访问的寄存器之间。 PRAM使用的示例包括：计算临时存储区域; 存储x86 VMX VMCS以响应VMREAD和VMWRITE宏指令; 实例化非用户可访问的存储，如x86 SMBASE寄存器; 以及容忍PRAM的附加访问延迟（例如IA32_SYSENTER_CS MSR）的x86 MSR的实例化。

公开(公告)号：US09378019B2

公开(公告)日：2016-06-28

申请号：US14007077

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30174 ,  G06F9/30189

摘要： A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.

摘要翻译： 微处理器指令转换器将条件加载指令转换成至少两个微指令。 无序执行管线执行微指令。 为了执行第一微指令，执行单元从寄存器堆的源寄存器接收源操作数，并使用源操作数响应地生成第一结果。 为了执行微指令，执行单元接收目的地寄存器的先前值和第一结果，并响应于从第一结果指定的存储器位置读取数据，并且如果满足条件则提供作为数据的第二结果， 这是以前的目标寄存器值，如果没有。 目的地寄存器的先前值包括通过执行作为目的地寄存器相对于第二微指令的最新的有序先前的写入器的微指令而产生的结果。

公开(公告)号：US20140013089A1

公开(公告)日：2014-01-09

申请号：US14007077

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30174 ,  G06F9/30189

摘要： A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.

摘要翻译： 微处理器指令转换器将条件加载指令转换成至少两个微指令。 无序执行管线执行微指令。 为了执行第一微指令，执行单元从寄存器堆的源寄存器接收源操作数，并使用源操作数响应地生成第一结果。 为了执行微指令，执行单元接收目的地寄存器的先前值和第一结果，并响应于从第一结果指定的存储器位置读取数据，并且如果满足条件则提供作为数据的第二结果， 这是以前的目标寄存器值，如果没有。 目的地寄存器的先前值包括通过执行作为目的地寄存器相对于第二微指令的最新的有序先前的写入器的微指令而产生的结果。

公开(公告)号：US07827390B2

公开(公告)日：2010-11-02

申请号：US12034503

申请日：2008-02-20

申请人： G. Glenn Henry ,  Colin Eddy ,  Rodney E. Hooker ,  Terry Parks

发明人： G. Glenn Henry ,  Colin Eddy ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/312

CPC分类号： G06F9/3824 ,  G06F9/26 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30123 ,  G06F9/30138 ,  G06F9/30174 ,  G06F9/3826

摘要： A microprocessor includes a private RAM (PRAM), for use by microcode, which is non-user-accessible and within its own distinct address space from the system memory address space. The PRAM is denser and slower than user-accessible registers of the microprocessor macroarchitecture, thereby enabling it to provide significantly more storage for microcode. The microinstruction set includes a microinstruction for loading data from the PRAM into the user-accessible registers, and a microinstruction for storing data from user-accessible registers to the PRAM. The microcode may also use the two microinstructions to load/store between the PRAM and non-user-accessible registers of the microarchitecture. Examples of PRAM uses include: computational temporary storage area; storage of x86 VMX VMCS in response to VMREAD and VMWRITE macroinstructions; instantiation of non-user-accessible storage, such as the x86 SMBASE register; and instantiation of x86 MSRs that tolerate the additional access latency of the PRAM, such as the IA32_SYSENTER_CS MSR.

摘要翻译： 微处理器包括专用RAM（PRAM），用于微码，这是非用户可访问的，并且在其自身与系统存储器地址空间不同的地址空间内。 PRAM比微处理器宏构架的用户可访问的寄存器更密集和更慢，从而使其能够为微码提供显着更多的存储。 微指令集包括用于将来自PRAM的数据加载到用户可访问寄存器中的微指令，以及用于将来自用户可访问寄存器的数据存储到PRAM的微指令。 微代码还可以使用两个微指令来加载/存储在微架构的PRAM和非用户可访问的寄存器之间。 PRAM使用的示例包括：计算临时存储区域; 存储x86 VMX VMCS以响应VMREAD和VMWRITE宏指令; 实例化非用户可访问的存储，如x86 SMBASE寄存器; 以及容忍PRAM的附加访问延迟（例如IA32_SYSENTER_CS MSR）的x86 MSR的实例化。

公开(公告)号：US09645822B2

公开(公告)日：2017-05-09

申请号：US14007097

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30076 ,  G06F9/30123 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196

摘要： An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.

公开(公告)号：US20140122843A1

公开(公告)日：2014-05-01

申请号：US14007097

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3017 ,  G06F9/30076 ,  G06F9/30123 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196

摘要： An instruction translator translates a conditional store instruction (specifying data register, base register, and offset register of the register file) into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives a base value and an offset from the register file and generates a first result as a function of the base value and offset. The first result specifies the memory location address. To execute a second microinstruction, an execution unit receives the first result and writes the first result to an allocated entry in the store queue if the condition flags satisfy the condition (the store queue subsequently writes the data to the memory location specified by the address), and otherwise kills the allocated store queue entry so that the store queue does not write the data to the memory location specified by the address.

摘要翻译： 指令翻译器将条件存储指令（指定寄存器文件的指定数据寄存器，基址寄存器和偏移寄存器）转换为至少两个微指令。 无序执行管线执行微指令。 为了执行第一微指令，执行单元从寄存器文件接收基值和偏移量，并且产生作为基值和偏移量的函数的第一结果。 第一个结果指定内存位置地址。 为了执行第二微指令，如果条件标志满足条件（存储队列随后将数据写入由地址指定的存储器位置），则执行单元接收第一结果并将第一结果写入存储队列中的已分配条目， ，否则将杀死所分配的存储队列条目，使得存储队列不将数据写入由地址指定的存储器位置。

公开(公告)号：US09244686B2

公开(公告)日：2016-01-26

申请号：US14007116

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/312 ,  G06F9/30 ,  G06F9/26 ,  G06F9/38 ,  G06F15/82

CPC分类号： G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

摘要： An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.

摘要翻译： 指令转换器接收指定条件，目标/数据寄存器，基址寄存器，偏移源和存储器寻址模式的条件加载/存储指令。 只有当条件标志满足条件时，指令才指示微处理器将数据从存储单元加载到目标寄存器（条件加载）中，或者将数据从数据寄存器（条件存储）​​存储到存储单元。 偏移源指定偏移量是立即值还是偏移量寄存器中的值。 寻址模式指定条件标志满足条件时是否更新基址寄存器。 指令翻译器将条件加载指令转换为多个微指令，其作为偏移源，寻址模式以及条件指令是条件加载还是存储指令的函数而变化。 无序执行流水线执行微指令以生成指令指定的结果。

公开(公告)号：US08566565B2

公开(公告)日：2013-10-22

申请号：US12170591

申请日：2008-07-10

申请人： Rodney E. Hooker ,  Colin Eddy ,  G. Glenn Henry

发明人： Rodney E. Hooker ,  Colin Eddy ,  G. Glenn Henry

IPC分类号： G06F17/00 ,  G06F9/445

CPC分类号： G06F1/3203 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/3814 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/3855 ,  G06F9/3869

摘要： A computing system includes a microprocessor that receives values for configuring operating modes thereof. A device driver monitors which software applications currently running on the microprocessor are in a predetermined list and responsively dynamically writes the values to the microprocessor to configure its operating modes. Examples of the operating modes the device driver may configure relate to the following: data prefetching; branch prediction; instruction cache eviction; instruction execution suspension; sizes of cache memories, reorder buffer, store/load/fill queues; hashing algorithms related to data forwarding and branch target address cache indexing; number of instruction translation, formatting, and issuing per clock cycle; load delay mechanism; speculative page tablewalks; instruction merging; out-of-order execution extent; caching of non-temporal hinted data; and serial or parallel access of an L2 cache and processor bus in response to an instruction cache miss.

摘要翻译： 计算系统包括接收用于配置其操作模式的值的微处理器。 设备驱动程序监视当前在微处理器上运行的软件应用程序处于预定列表中并且响应地动态地将值写入微处理器以配置其操作模式。 设备驱动程序可以配置的操作模式的示例涉及以下内容：数据预取; 分支预测; 指令缓存驱逐; 指令执行暂停; 高速缓冲存储器的大小，重新排序缓冲器，存储/加载/填充队列; 与数据转发和分支目标地址缓存索引相关的散列算法; 每个时钟周期的指令翻译，格式化和发布的数量; 负载延迟机制; 投机页面 指令合并 无序执行程度; 缓存非时间暗示数据; 以及响应于指令高速缓存未命中的L2高速缓存和处理器总线的串行或并行访问。

公开(公告)号：US20100306503A1

公开(公告)日：2010-12-02

申请号：US12781337

申请日：2010-05-17

申请人： G. Glenn Henry ,  Colin Eddy ,  Rodney E. Hooker

发明人： G. Glenn Henry ,  Colin Eddy ,  Rodney E. Hooker

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/325 ,  G06F9/383 ,  G06F2212/6028

摘要： A microprocessor includes a cache memory, an instruction set having first and second prefetch instructions each configured to instruct the microprocessor to prefetch a cache line of data from a system memory into the cache memory, and a memory subsystem configured to execute the first and second prefetch instructions. For the first prefetch instruction the memory subsystem is configured to forego prefetching the cache line of data from the system memory into the cache memory in response to a predetermined set of conditions. For the second prefetch instruction the memory subsystem is configured to complete prefetching the cache line of data from the system memory into the cache memory in response to the predetermined set of conditions.

摘要翻译： 微处理器包括高速缓存存储器，指令集具有第一和第二预取指令，每个指令都被配置为指示微处理器将数据的高速缓存行从系统存储器预取到高速缓冲存储器中;以及存储器子系统，被配置为执行第一和第二预取 说明。 对于第一预取指令，存储器子系统被配置为响应于预定的一组条件而将数据的高速缓存行从系统存储器预取到高速缓冲存储器中。 对于第二预取指令，存储器子系统被配置为响应于预定的条件集合来完成从系统存储器将数据的高速缓存行预取到高速缓冲存储器中。