公开(公告)号：US09501286B2

公开(公告)日：2016-11-22

申请号：US12609169

申请日：2009-10-30

申请人： Gerard M. Col ,  Colin Eddy ,  Rodney E. Hooker

发明人： Gerard M. Col ,  Colin Eddy ,  Rodney E. Hooker

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/08

CPC分类号： G06F9/3875 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3893 ,  G06F12/0875

摘要： A superscalar pipelined microprocessor includes a register set defined by its instruction set architecture, a cache memory, execution units, and a load unit, coupled to the cache memory and distinct from the other execution units. The load unit comprises an ALU. The load unit receives an instruction that specifies a memory address of a source operand, an operation to be performed on the source operand to generate a result, and a destination register of the register set to which the result is to be stored. The load unit reads the source operand from the cache memory. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The load unit outputs the result for subsequent retirement to the destination register.

摘要翻译： 超标量流水线微处理器包括由其指令集架构定义的寄存器组，高速缓冲存储器，执行单元和负载单元，耦合到高速缓冲存储器并且与其他执行单元不同。 负载单元包括一个ALU。 加载单元接收指定源操作数的存储器地址的指令，要在源操作数上执行的用于生成结果的操作以及要存储结果的寄存器集的目标寄存器。 加载单元从缓存中读取源操作数。 ALU对源操作数执行操作以生成结果，而不是将源操作数转发到微处理器的任何其他执行单元，以对源操作数执行操作以生成结果。 加载单元将结果退出到目的地寄存器。

公开(公告)号：US09244686B2

公开(公告)日：2016-01-26

申请号：US14007116

申请日：2012-04-06

申请人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/312 ,  G06F9/30 ,  G06F9/26 ,  G06F9/38 ,  G06F15/82

CPC分类号： G06F9/441 ,  G06F9/265 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/3802 ,  G06F9/4401 ,  G06F9/4403 ,  G06F15/82

摘要： An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.

摘要翻译： 指令转换器接收指定条件，目标/数据寄存器，基址寄存器，偏移源和存储器寻址模式的条件加载/存储指令。 只有当条件标志满足条件时，指令才指示微处理器将数据从存储单元加载到目标寄存器（条件加载）中，或者将数据从数据寄存器（条件存储）​​存储到存储单元。 偏移源指定偏移量是立即值还是偏移量寄存器中的值。 寻址模式指定条件标志满足条件时是否更新基址寄存器。 指令翻译器将条件加载指令转换为多个微指令，其作为偏移源，寻址模式以及条件指令是条件加载还是存储指令的函数而变化。 无序执行流水线执行微指令以生成指令指定的结果。

公开(公告)号：US08090931B2

公开(公告)日：2012-01-03

申请号：US12233261

申请日：2008-09-18

申请人： Gerard M. Col ,  G. Glenn Henry ,  Rodney E. Hooker ,  Terry Parks

发明人： Gerard M. Col ,  G. Glenn Henry ,  Rodney E. Hooker ,  Terry Parks

IPC分类号： G06F9/34

CPC分类号： G06F9/30043 ,  G06F9/30174 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3857

摘要： A microprocessor includes an instruction translator that translates PUSHF, POP, and MOVSB x86 macroinstructions into multiple microinstructions that include a fused store microinstruction. For PUSHF, first and second microinstructions moves the x86 EFLAGS register into and mask off bits in a temporary register, and the fused store microinstruction stores it to a memory location. For POP, a first microinstruction loads a first memory location value into a temporary register and the fused store microinstruction stores it to the second memory location. For MOVSB, the first microinstruction loads a first memory location operand into a temporary register and the fused store microinstruction stores it to a second memory location. A reorder buffer receives the fused store microinstruction into exactly one entry. In response to the fused store microinstruction, an instruction dispatcher dispatches store address and store data microinstructions, neither of which occupies a reorder buffer entry, to different respective execution units.

摘要翻译： 微处理器包括将PUSHF，POP和MOVSB x86宏指令转换成包括融合存储微指令的多个微指令的指令转换器。 对于PUSHF，第一和第二微指令将x86 EFLAGS寄存器移入临时寄存器中并将其屏蔽，并且融合存储微指令将其存储到存储器位置。 对于POP，第一微指令将第一存储器位置值加载到临时寄存器中，并且融合存储器微指令将其存储到第二存储器位置。 对于MOVSB，第一微指令将第一存储器位置操作数加载到临时寄存器中，并且熔接存储器微指令将其存储到第二存储器位置。 重新排序缓冲器将融合存储微指令接收到正好一个条目。 响应于融合存储微指令，指令分派器调度存储地址并存储数据微指令（这两个微指令都不占用重排序缓冲器入口）到不同的各个执行单元。

公开(公告)号：US08069339B2

公开(公告)日：2011-11-29

申请号：US12469430

申请日：2009-05-20

申请人： G. Glenn Henry ,  Terry Parks ,  Gerard M. Col

发明人： G. Glenn Henry ,  Terry Parks ,  Gerard M. Col

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/30116 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30185

摘要： A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plurality of condition code flags based on a result of the first instruction. The first instruction includes a field for indicating whether to update the plurality of condition code flags of the architectural or non-architectural register. A second instruction of the microarchitectural instruction set instructs the microprocessor to conditionally perform an operation based on one of the plurality of condition code flags. The second instruction includes a field for indicating whether to use the one of the plurality of condition code flags of the architectural or non-architectural register to determine whether to perform the operation.

摘要翻译： 微处理器包括架构寄存器和非架构寄存器，每个都具有多个条件码标志。 微处理器的微架构指令集的第一指令指示微处理器基于第一指令的结果来更新多个条件代码标志。 第一指令包括用于指示是否更新架构或非架构寄存器的多个条件代码标志的字段。 微架构指令集的第二指令指示微处理器基于多个条件代码标志之一有条件地执行操作。 第二指令包括用于指示是否使用架构或非架构寄存器的多个条件代码标志中的一个来确定是否执行操作的字段。

公开(公告)号：US20110035570A1

公开(公告)日：2011-02-10

申请号：US12609193

申请日：2009-10-30

申请人： Gerard M. Col ,  Colin Eddy ,  Rodney E. Hooker

发明人： Gerard M. Col ,  Colin Eddy ,  Rodney E. Hooker

IPC分类号： G06F9/30 ,  G06F12/08 ,  G06F9/302 ,  G06F9/305

CPC分类号： G06F9/3875 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3893 ,  G06F12/0875

摘要： A superscalar pipelined microprocessor includes a register set defined by an instruction set architecture of the microprocessor, execution units, and a store unit, coupled to the cache memory and distinct from the other execution units of the microprocessor. The store unit comprises an ALU. The store unit receives an instruction that specifies a source register of the register set and an operation to be performed on a source operand to generate a result. The store unit reads the source operand from the source register. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The store unit operatively writes the result to the cache memory.

摘要翻译： 超标量流水线微处理器包括由微处理器的指令集架构定义的寄存器组，执行单元和存储单元，其耦合到高速缓冲存储器并且与微处理器的其他执行单元不同。 存储单元包括ALU。 存储单元接收指定寄存器组的源寄存器和要对源操作数执行的操作以产生结果的指令。 存储单元从源寄存器读取源操作数。 ALU对源操作数执行操作以生成结果，而不是将源操作数转发到微处理器的任何其他执行单元，以对源操作数执行操作以生成结果。 存储单元可操作地将结果写入缓存存储器。

公开(公告)号：US20100306506A1

公开(公告)日：2010-12-02

申请号：US12582975

申请日：2009-10-21

申请人： Rodney E. Hooker ,  Gerard M. Col ,  Bryan Wayne Pogor

发明人： Rodney E. Hooker ,  Gerard M. Col ,  Bryan Wayne Pogor

IPC分类号： G06F9/38

CPC分类号： G06F9/3842 ,  G06F9/3806 ,  G06F9/3861

摘要： A pipelined out-of-order execution in-order retire microprocessor includes a branch predictor that predicts a target address of a branch instruction, a fetch unit that fetches instructions at the predicted target address, and an execution unit that: resolves a target address of the branch instruction and detects that the predicted and resolved target addresses are different; determines whether there is an unretired instruction that must be corrected and that is older in program order than the branch instruction, in response to detecting that the predicted and resolved target addresses are different; execute the branch instruction by flushing instructions fetched at the predicted target address and causing the fetch unit to fetch from the resolved target address, if there is not an unretired instruction that must be corrected and that is older in program order than the branch instruction; and otherwise, refrain from executing the branch instruction.

摘要翻译： 流水线式无序执行按顺序退出微处理器包括预测分支指令的目标地址的分支预测器，取得预测目标地址的指令的获取单元，以及执行单元，其解析目标地址 分支指令，并检测预测和解决的目标地址不同; 响应于检测到预测和解析的目标地址不同，确定是否存在必须被校正并且在程序顺序中比分支指令更旧的未命令指令; 通过刷新在预测目标地址处获得的指令来执行分支指令，并且如果不存在必须被校正并且在程序顺序中比分支指令更老的指令，则从解决的目标地址获取提取单元; 否则，不执行分支指令。

公开(公告)号：US20100299504A1

公开(公告)日：2010-11-25

申请号：US12469430

申请日：2009-05-20

申请人： G. Glenn Henry ,  Terry Parks ,  Gerard M. Col

发明人： G. Glenn Henry ,  Terry Parks ,  Gerard M. Col

IPC分类号： G06F9/30

CPC分类号： G06F9/30116 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/30185

摘要： A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plurality of condition code flags based on a result of the first instruction. The first instruction includes a field for indicating whether to update the plurality of condition code flags of the architectural or non-architectural register. A second instruction of the microarchitectural instruction set instructs the microprocessor to conditionally perform an operation based on one of the plurality of condition code flags. The second instruction includes a field for indicating whether to use the one of the plurality of condition code flags of the architectural or non-architectural register to determine whether to perform the operation.

摘要翻译： 微处理器包括架构寄存器和非架构寄存器，每个都具有多个条件码标志。 微处理器的微架构指令集的第一指令指示微处理器基于第一指令的结果来更新多个条件代码标志。 第一指令包括用于指示是否更新架构或非架构寄存器的多个条件代码标志的字段。 微架构指令集的第二指令指示微处理器基于多个条件代码标志之一有条件地执行操作。 第二指令包括用于指示是否使用架构或非架构寄存器的多个条件代码标志中的一个来确定是否执行操作的字段。

公开(公告)号：US20100205406A1

公开(公告)日：2010-08-12

申请号：US12369132

申请日：2009-02-11

申请人： Rodney E. Hooker ,  Gerard M. Col ,  Terry Parks

发明人： Rodney E. Hooker ,  Gerard M. Col ,  Terry Parks

IPC分类号： G06F9/312 ,  G06F9/315 ,  G06F9/30

CPC分类号： G06F9/30076 ,  G06F9/3013 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842

摘要： An out-of-order execution microprocessor executes an architectural segment register-loading instruction that instructs the microprocessor to load a new value into an architectural segment register of the microprocessor. A comparator compares the new value specified by the architectural segment register-loading instruction with a current contents of the architectural segment register. A control unit causes to be re-executed using the new value all instructions in the microprocessor that used the current architectural segment register contents as a source operand and that are newer in program order than the architectural segment register-loading instruction whenever the comparator indicates the new value does not equal the current contents. An instruction scheduler retrieves the current contents and issues for execution instructions that use the retrieved current contents, even though the instructions are newer in program order than the register-loading instruction and the register-loading instruction has not yet written the new value to the architectural segment register.

摘要翻译： 无序执行微处理器执行体系结构段寄存器加载指令，其指示微处理器将新值加载到微处理器的架构段寄存器中。 比较器将结构化段寄存器加载指令指定的新值与架构段寄存器的当前内容进行比较。 控制单元导致使用新值将微处理器中的所有指令重新执行，该指令使用当前的体系结构段寄存器内容作为源操作数，并且只要比较器指示结构段寄存器加载指令，则程序顺序比结构化段寄存器加载指令更新 新值不等于当前内容。 指令调度器检索使用所检索的当前内容的执行指令的当前内容和问题，即使指令在程序顺序中比寄存器加载指令更新，并且寄存器加载指令尚未将新值写入架构 段寄存器。

公开(公告)号：US20090204800A1

公开(公告)日：2009-08-13

申请号：US12100616

申请日：2008-04-10

申请人： Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

发明人： Rodney E. Hooker ,  Gerard M. Col ,  Colin Eddy

IPC分类号： G06F9/22

CPC分类号： G06F9/3004 ,  G06F9/30087 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855

摘要： The microprocessor includes an instruction translator that translates a macroinstruction of a macroinstruction set in its macroarchitecture into exactly three microinstructions to perform a read/modify/write operation on a memory operand. The first microinstruction instructs the microprocessor to load the memory operand into the microprocessor from a memory location and to calculate a destination address of the memory location. The second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result. The third microinstruction instructs the microprocessor to write the result to the memory location whose destination address is calculated by the first microinstruction. A first execution unit receives the first microinstruction and responsively loads the memory operand into the microprocessor from the memory location, and a second distinct execution unit also receives the first microinstruction and responsively calculates the destination address of the memory location.

摘要翻译： 微处理器包括一个指令转换器，它将宏构造中的宏指令集的宏指令转换成三个微指令，以对存储器操作数执行读/修/写操作。 第一微指令指示微处理器从存储器位置将存储器操作数加载到微处理器中并计算存储器位置的目的地地址。 第二微指令指示微处理器对加载的存储器操作数执行算术或逻辑运算以产生结果。 第三个微指令指示微处理器将结果写入由第一个微指令计算目标地址的存储单元。 第一执行单元接收第一微指令并且响应地将存储器操作数从存储器位置加载到微处理器中，并且第二不同执行单元还接收第一微指令并且响应地计算存储器位置的目的地地址。

公开(公告)号：US07100024B2

公开(公告)日：2006-08-29

申请号：US10771678

申请日：2004-02-04

申请人： Gerard M. Col

发明人： Gerard M. Col

IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F15/00

CPC分类号： G06F9/3861 ,  G06F9/30094 ,  G06F9/3848

摘要： An apparatus and method for generating early status flags in a pipeline microprocessor is disclosed. The apparatus includes early status flag generation logic that receives an instruction, an early result of the instruction, and a valid indicator of the early result and responsively generates the early flags. If the instruction is flag-modifying, then the early status flags are stored in an early flags register. The early flags in the register are invalidated if the early result from which they are generated is invalid. The early status flags and associated valid indicator may be employed by subsequent conditional instructions for early execution to avoid delay in waiting for the architected status flag values to be generated by execution units later in the pipeline. The early flags are revalidated if all flags-modifying instructions in pipeline stages below the early flag generation logic, if any, have already updated the architected status flags.

摘要翻译： 公开了一种用于在流水线微处理器中产生早期状态标志的装置和方法。 该装置包括接收指令的早期状态标志生成逻辑，指令的早期结果和早期结果的有效指示符，并且响应地生成早期标志。 如果指令是标志修改，则早期状态标志存储在早期标志寄存器中。 如果生成的早期结果无效，则寄存器中的早期标志无效。 早期状态标志和相关联的有效指示符可以由用于早期执行的后续条件指令来采用，以避免在稍后的流水线中执行单元等待构造状态标志值的延迟。 如果在早期标志生成逻辑之下的流水线阶段中的所有标志修改指令（如果有的话）已经更新了架构状态标志，则早期标志被重新验证。