公开(公告)号：US6097767A

公开(公告)日：2000-08-01

申请号：US61252

申请日：1998-04-17

Applicant: William Lo ,  Yi Cheng ,  Bin Guo

Inventor： William Lo ,  Yi Cheng ,  Bin Guo

IPC: H04B3/14 ,  H03D3/18

CPC classification number: H04B3/145 ,  H04B3/148

Abstract: An optimum equalizer setting is determined for a signal equalizer in a network receiver by successively setting the equalizer to different predetermined settings, detecting timing correlation results between the equalized signal and a recovered clock in a digital phase locked loop, and determining a normalized distribution result for each of the predetermined equalizer settings based on the timing correlation results. The equalizer setting having the minimum normalized distribution result can then be selected as the optimum equalizer setting. Use of the correlation result from the phase locked loop enables the equalizer controller determining the optimum equalizer setting to determine the setting using a closed-loop setting. Hence, the equalizer controller can effectively determine the equalizer setting that causes the minimum amount of jitter in the phase locked loop.

Abstract translation: 通过将均衡器连续地设置为不同的预定设置，检测均衡信号和数字锁相环中的恢复时钟之间的定时相关结果，确定网络接收机中的信号均衡器的最佳均衡器设置，并且确定归一化分布结果 基于定时相关结果的每个预定均衡器设置。 然后可以选择具有最小归一化分布结果的均衡器设置作为最佳均衡器设置。 使用相位锁定环路的相关结果使均衡器控制器能够确定最佳均衡器设置，以使用闭环设置来确定设置。 因此，均衡器控制器可以有效地确定在锁相环中产生最小抖动量的均衡器设置。

公开(公告)号：US5995514A

公开(公告)日：1999-11-30

申请号：US787152

申请日：1997-01-31

Applicant: William Lo

Inventor： William Lo

IPC: H04L12/44 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08 ,  H04L12/00

CPC classification number: H04L49/901 ,  H04L12/44 ,  H04L29/06 ,  H04L49/90 ,  H04L69/323

Abstract: A reversible media independent interface (MII) circuit is disclosed. The MII circuit comprises a first management circuit and a second management circuit. The first management circuit is operating in a first mode, the first mode being an interface between the MII and a media access control (AC) device. The second management circuit is operating in a second mode, the second mode being an interface between the MII and a physical layer (PHY) device. The MII circuit also includes a plurality of signals being provided to and sent from the MII circuit. A first portion of the plurality of signals are operable within either a physical layer device in a first mode or a media access control device in a second mode. A second portion of the plurality of the signals are provided the first management circuit and the second management circuit. The second portion of the plurality of signals are modifiable such that they are operable within the first management circuit in the first mode and are operable within the second management circuit in the second mode. In one embodiment by allowing the portion of the plurality of signals to be in a first and second mode (i.e., forward or reverse). The MII interface can be reversed such that it looks likes the MII interface found on either the PHY or MAC device. Accordingly, then either the MAC device can then be connected directly to the repeater without any PHYs or vice versa.

Abstract translation: 公开了一种可逆介质独立接口（MII）电路。 MII电路包括第一管理电路和第二管理电路。 第一管理电路以第一模式操作，第一模式是MII与媒体访问控制（AC）设备之间的接口。 第二管理电路以第二模式操作，第二模式是MII与物理层（PHY）设备之间的接口。 MII电路还包括提供给MII电路并从MII电路发送的多个信号。 多个信号的第一部分可在第一模式中的物理层设备或第二模式中的媒体访问控制设备中操作。 多个信号的第二部分被提供在第一管理电路和第二管理电路中。 多个信号的第二部分是可修改的，使得它们在第一模式下在第一管理电路内可操作，并且在第二模式中可在第二管理电路内操作。 在一个实施例中，允许多个信号的一部分处于第一和第二模式（即，正向或反向）。 MII接口可以反转，使其看起来像PHY或MAC设备上发现的MII接口。 因此，则MAC设备然后可以直接连接到中继器，而不需要任何PHY，反之亦然。

公开(公告)号：US08885664B1

公开(公告)日：2014-11-11

申请号：US13591954

申请日：2012-08-22

Applicant: William Lo ,  Brett A. McClellan

Inventor： William Lo ,  Brett A. McClellan

IPC: H04W4/00 ,  H04J3/18

CPC classification number: H04L12/28 ,  H04J3/18 ,  H04L1/00 ,  H04L1/08 ,  H04L12/413 ,  H04L25/05

Abstract: A method for converting a data stream from a first rate to a second rate NA times greater than the first rate, such that the converted data stream conforms to a coding requirement that symbols be arranged in units of symbol length M, includes receiving, at the first rate, a data packet, and an inter-packet gap containing Y1 idle symbols, generating NA repetitions of each data symbol of the data packet, determining whether replicating each symbol of the inter-packet gap NA times would violate the coding requirement, and, at least partially in response to determining that replicating each symbol of the inter-packet gap NA times would violate the requirement, generating greater than or less than Y1*NA idle symbols. The method also includes outputting, at the second rate, the generated NA repetitions of each data symbol and the generated idle symbols.

Abstract translation: 一种用于将数据流从第一速率转换为大于第一速率NA的第二速率的方法，使得转换的数据流符合符号以符号长度M为单位排列的编码要求，包括在 第一速率，数据分组和包含Y1空闲符号的分组间间隔，产生数据分组的每个数据符号的NA重复，确定是否复制分组间间隙NA的每个符号将违反编码要求，以及 至少部分地响应于确定复制每个分组间间隙的每个符号NA次将违反要求，生成大于或小于Y1 * NA空闲符号。 该方法还包括以第二速率输出每个数据符号的所生成的NA重复和产生的空闲符号。

公开(公告)号：US08829917B1

公开(公告)日：2014-09-09

申请号：US13470893

申请日：2012-05-14

Applicant: William Lo ,  Yiqing Guo ,  Tak Tsui ,  Tsin-Ho Leung ,  Runsheng He ,  Eric Janofsky

Inventor： William Lo ,  Yiqing Guo ,  Tak Tsui ,  Tsin-Ho Leung ,  Runsheng He ,  Eric Janofsky

IPC: G01R31/11

CPC classification number: H04L43/50 ,  G01R31/11 ,  H04L12/10

Abstract: A physical layer device configured to interface with a plurality of pairs of wires. The physical layer device includes a cable test module configured to transmit a pulse over the plurality of pairs of wires, measure a reflection of the pulse as received from the plurality of pairs of wires, and determine whether a short circuit exists in one of the plurality of pairs of wires based on the measure of the reflection of the pulse. An autonegotiation module is configured to perform autonegotiation to establish a link at a particular speed over the plurality of pairs of wires. The particular speed at which the link is established over the plurality of pairs of wires is based, at least in part, on whether a short circuit exists in one of the plurality of pairs of wires as determined by the cable test module.

Abstract translation: 物理层设备，被配置为与多对线对接口。 物理层设备包括：电缆测试模块，被配置为在所述多对导线上传输脉冲，测量从所述多对导线接收的所述脉冲的反射，并且确定所述多个导线之一中是否存在短路 的基于脉冲反射测量的电线对。 自动协商模块被配置为执行自动协商以在多对线路上以特定速度建立链路。 至少部分地基于由电缆测试模块确定的多对线中的一条线路是否存在短路，在多对线路上建立链路的特定速度是基于的。

公开(公告)号：US08824502B2

公开(公告)日：2014-09-02

申请号：US13585216

申请日：2012-08-14

Applicant: Ozdal Barkan ,  Nafea Bishara ,  William Lo

Inventor： Ozdal Barkan ,  Nafea Bishara ,  William Lo

IPC: H04L12/28

CPC classification number: H04L12/4013 ,  H04L1/0002 ,  H04L5/1446 ,  H04L12/413 ,  H04L47/10 ,  H04L47/22 ,  H04L49/3054 ,  H04L49/352 ,  H04L49/90 ,  H04L49/9078 ,  Y02D50/10

Abstract: A network interface module includes a physical layer module and a data rate module. The physical layer module is configured to transmit first signals to a network device via a cable at a first data rate while conforming to Ethernet baseband characteristics for the first data rate, and at least one of determine a characteristic of the cable, or perform an autonegotiation process with the network device. The data rate module is configured to select a second data rate based on at least one of the characteristic of the cable, or results of the autonegotiation process. The second data rate is slower than the first data rate. The physical layer module is configured to transmit second signals to the network device at the second data rate while conforming to the Ethernet baseband characteristics for the first data rate.

Abstract translation: 网络接口模块包括物理层模块和数据速率模块。 物理层模块被配置为通过电缆以第一数据速率将第一信号发送到网络设备，同时符合用于第一数据速率的以太网基带特性，并且确定电缆的特性中的至少一个，或执行自动协商 与网络设备进程。 数据速率模块被配置为基于电缆的特征中的至少一个或自动协商过程的结果来选择第二数据速率。 第二数据速率比第一数据速率慢。 物理层模块被配置为以符合第一数据速率的以太网基带特性的第二数据速率向网络设备发送第二信号。

公开(公告)号：US08612629B1

公开(公告)日：2013-12-17

申请号：US13245513

申请日：2011-09-26

Applicant: William Lo ,  Nafea Bishara

Inventor： William Lo ,  Nafea Bishara

IPC: G06F15/16

CPC classification number: H04L65/60 ,  H04L49/3054 ,  H04L49/352

Abstract: A network device including a media access control (MAC) device, and a physical layer (PHY) device. The physical layer (PHY) device is in communication with the MAC device via (i) a first serializer/deserializer (SERDES) and (ii) a second SERDES, wherein the first SERDES and the second SERDES operate at a fixed data rate. The MAC device comprises a translator configured to, in response to the MAC device operating at a data rate that is less than the fixed data rate, i) append a predetermined number of bits to data in a first data stream to be transmitted to the PHY device, and ii) subsequent to appending the predetermined number of bits to the data in the first data stream, duplicate the data having the appended predetermined number of bits to generate a second data stream at the fixed data rate.

Abstract translation: 一种包括媒体接入控制（MAC）设备和物理层（PHY）设备的网络设备。 物理层（PHY）设备通过（i）第一串行器/解串器（SERDES）和（ii）第二SERDES与MAC设备通信，其中第一SERDES和第二SERDES以固定数据速率操作。 MAC设备包括翻译器，其被配置为响应于MAC设备以小于固定数据速率的数据速率操作，i）将预定数量的比特附加到要发送到PHY的第一数据流中的数据 设备，以及ii）在将预定数量的比特附加到第一数据流中的数据之后，复制具有附加的预定比特数的数据，以产生固定数据速率的第二数据流。

公开(公告)号：US08582434B1

公开(公告)日：2013-11-12

申请号：US13023389

申请日：2011-02-08

Applicant: William Lo

Inventor： William Lo

IPC: G01R31/06

CPC classification number: H04L12/10 ,  H04L12/40136 ,  H04L12/4625 ,  H04L12/5692 ,  H04L47/70 ,  Y02D50/10

Abstract: A media selection system includes a plurality of media ports. Each of the plurality of media ports is coupled to a corresponding physical medium, and each of the plurality of media ports is configured to generate an activity signal and a link status signal. A priority storage module is configured to contain priority information, which sets forth a priority for establishing a link through each of the plurality of media ports. A media selector module is configured to select a first media port through which a link will be maintained based on the link status signal generated by each of the plurality of media ports and the priority information. The media selector module is further configured to block all other links through media ports of the plurality of media ports other than the first media port.

Abstract translation: 媒体选择系统包括多个媒体端口。 多个媒体端口中的每一个耦合到对应的物理介质，并且多个媒体端口中的每一个被配置为生成活动信号和链路状态信号。 优先级存储模块被配置为包含优先级信息，其中列出了通过多个媒体端口中的每一个来建立链路的优先级。 媒体选择器模块被配置为基于由多个媒体端口中的每个媒体端口和优先级信息生成的链路状态信号来选择将维护链路的第一媒体端口。 媒体选择器模块还被配置为通过除第一媒体端口之外的多个媒体端口的媒体端口来阻止所有其他链路。

公开(公告)号：US08345673B1

公开(公告)日：2013-01-01

申请号：US11971612

申请日：2008-01-09

Applicant: William Lo ,  Ozdal Barkan

Inventor： William Lo ,  Ozdal Barkan

IPC: H04L12/50 ,  H04L12/28 ,  H04L12/66 ,  H04Q11/00 ,  H04J3/16 ,  G06F15/173 ,  G06F1/00 ,  G06F15/16

CPC classification number: G06F1/26 ,  G06F1/3209 ,  G06F1/3287 ,  H04L29/08099 ,  H04Q2213/13097 ,  H04Q2213/1332 ,  H04Q2213/13362 ,  Y02D10/171 ,  Y02D50/20

Abstract: Apparatus having corresponding methods comprise: a physical-layer input circuit to receive first signals representing first data; a first serializer to transmit a serial stream of the first data; and a magic packet circuit to generate a magic packet signal when the first data includes a magic packet.

Abstract translation: 具有相应方法的装置包括：物理层输入电路，用于接收表示第一数据的第一信号; 第一串行器，用于发送第一数据的串行流; 以及魔术分组电路，用于当第一数据包括魔术分组时产生魔术分组信号。

公开(公告)号：US20120314716A1

公开(公告)日：2012-12-13

申请号：US13585216

申请日：2012-08-14

Applicant: Ozdal Barkan ,  Nafea Bishara ,  William Lo

Inventor： Ozdal Barkan ,  Nafea Bishara ,  William Lo

IPC: H04L12/56

CPC classification number: H04L12/4013 ,  H04L1/0002 ,  H04L5/1446 ,  H04L12/413 ,  H04L47/10 ,  H04L47/22 ,  H04L49/3054 ,  H04L49/352 ,  H04L49/90 ,  H04L49/9078 ,  Y02D50/10

Abstract: A physical-layer device includes a cable measurement module, a data rate module and a physical-layer device core. The cable measurement module measures characteristics of a cable. The data rate module (i) selects a data rate divisor N based on the characteristics of the cable, and (ii) reduces a rate of a first clock based on the data rate divisor N, where N is greater than 1. The physical-layer device core includes: a transmit module that transmits first signals over the cable at a data rate of M/N Gbps based on the rate of the first clock, where M is an integer; and a receive module that receives second signals over the cable at the data rate of M/N Gbps based on the rate of the first clock. The first and second signals conform to 1000BASE-T when M=1. The first and signals conform to 10GBASE-T when M=10.

Abstract translation: 物理层设备包括电缆测量模块，数据速率模块和物理层设备核心。 电缆测量模块测量电缆的特性。 数据速率模块（i）基于电缆的特性来选择数据速率因数N，并且（ii）基于数据速率除数N降低第一时钟的速率，其中N大于1。 层设备核心包括：发射模块，其基于第一时钟的速率以M / N Gbps的数据速率通过电缆发送第一信号，其中M是整数; 以及接收模块，其以基于第一时钟的速率的M / N Gbps的数据速率通过电缆接收第二信号。 当M = 1时，第一和第二信号符合1000BASE-T。 当M = 10时，第一个和信号符合10GBASE-T。

公开(公告)号：US08327195B1

公开(公告)日：2012-12-04

申请号：US13300354

申请日：2011-11-18

Applicant: Haoli Qian ,  William Lo ,  Runsheng He ,  Jeffrey Choun ,  Ping Zheng ,  Hui Wang ,  Yi-Chun Chen ,  Chee Hoe Chu

Inventor： Haoli Qian ,  William Lo ,  Runsheng He ,  Jeffrey Choun ,  Ping Zheng ,  Hui Wang ,  Yi-Chun Chen ,  Chee Hoe Chu

IPC: G06F11/00 ,  H03H7/30

CPC classification number: H04L25/03019 ,  H04L1/203 ,  H04L25/03057

Abstract: A system including a summer, a comparator, a zero-crossing module, and a control module. The summer is configured to (i) receive a data input signal, and (ii) generate an equalized signal in response to the data input signal. The comparator is configured to generate a recovered data signal in response to the equalized signal. The zero-crossing module is configured to generate a zero-crossing signal in response to the equalized signal. The control module is configured to generate eye information in response to i) the recovered data signal and ii) the zero-crossing signal. The eye information includes characteristic data associated with the recovered data signal, and the characteristic data when plotted provides an eye diagram.

Abstract translation: 包括加法器，比较器，过零模块和控制模块的系统。 夏天被配置为（i）接收数据输入信号，以及（ii）响应于数据输入信号产生均衡的信号。 比较器被配置为响应于均衡的信号产生恢复的数据信号。 过零模块被配置为响应于均衡信号产生过零信号。 控制模块被配置为响应于i）恢复的数据信号和ii）过零信号来生成眼睛信息。 眼睛信息包括与恢复的数据信号相关联的特征数据，并且绘制时的特征数据提供眼图。