SYSTEM AND METHOD FOR RATE ADAPTATION OF PACKET-ORIENTED CLIENT DATA FOR TRANSMISSION OVER A METRO TRANSPORT NETWORK (MTN)

    公开(公告)号:US20230318934A1

    公开(公告)日:2023-10-05

    申请号:US18116293

    申请日:2023-03-01

    CPC classification number: H04L41/34 H04L45/34 H04L69/22

    Abstract: A system and method for performing rate adaptation of sub1G packet-oriented client signals for transmission over a Metro Transport Network (MTN) by forming a 64B/66B-encoded client signal from individual client packets of the sub1G packet-oriented client signal and the idle blocks within an inter-packet gap (IPG), inserting thread operations, administration and maintenance (ThOAM) overhead to generate a 64B/66B-encoded client thread signal, performing an idle mapping procedure (IMP) to generate a rate adapted 64B/66B-encoded client thread signal, defining a plurality of pseudo-Ethernet packets in an MTN path, defining a thread channel within the plurality of pseudo-Ethernet packets and mapping the rate adapted 64B/66B-encoded client thread signal into the defined thread channel within the plurality of pseudo-Ethernet packets to generate an MTN path signal for transmission to an intermediate node or a sink mode.

    Method and apparatus for conveying clock-related information from a timing device

    公开(公告)号:US11736065B2

    公开(公告)日:2023-08-22

    申请号:US17884889

    申请日:2022-08-10

    CPC classification number: H03B5/36 H03B5/04 H03K3/017 H03K19/1737

    Abstract: A timing device includes an oven having a chamber, a crystal oscillator disposed in the chamber that generates a clock signal, and one or more sensors to generate operational characteristic signals indicative of respective operational characteristics of the crystal oscillator or the oven. The timing device includes a plurality of I/O connections and an IC device. The IC device includes processing logic to generate information that indicates how the generated clock signal is to be modified and a modulator coupled to the processing logic and the crystal oscillator. The modulator modulates the generated clock signal in relation to the information to generate a modulated clock signal indicative of the one or more operational characteristics of the crystal oscillator or the oven. The modulator outputs the modulated clock signal over a single one of the plurality of I/O connections.

    Method and Apparatus for Conveying Clock-Related Information from a Timing Device

    公开(公告)号:US20230113151A1

    公开(公告)日:2023-04-13

    申请号:US17884889

    申请日:2022-08-10

    Abstract: A timing device includes an oven having a chamber, a crystal oscillator disposed in the chamber that generates a clock signal, and one or more sensors to generate operational characteristic signals indicative of respective operational characteristics of the crystal oscillator or the oven. The timing device includes a plurality of I/O connections and an IC device. The IC device includes processing logic to generate information that indicates how the generated clock signal is to be modified and a modulator coupled to the processing logic and the crystal oscillator. The modulator modulates the generated clock signal in relation to the information to generate a modulated clock signal indicative of the one or more operational characteristics of the crystal oscillator or the oven. The modulator outputs the modulated clock signal over a single one of the plurality of I/O connections.

    Method and Apparatus for Decoding with Trapped-Block Management

    公开(公告)号:US20230094363A1

    公开(公告)日:2023-03-30

    申请号:US17952240

    申请日:2022-09-24

    Abstract: A method and apparatus for decoding in which a first failed decode operation is performed on raw bit values of a FEC block by a LDPC decoder. When the FEC block is determined to be a trapped block an updated LLR map is generated; the updated LLR map and either the raw bit values of the FEC block or a failed-decode-output-block from a previous failed decode operation on the trapped block are provided to the LDPC decoder; a decode operation of the LDPC decoder is performed using the updated LLR map on the bit values of the FEC block or the failed-decode-output-block from the previous failed decode operation; and the generating, the providing and the performing are repeated until the decode operation is successful or until a predetermined number of trapped-block-decoding iterations have been performed. When the decode operation is successful in decoding the FEC block the codeword is output.

    SYSTEM AND METHOD FOR PERFORMING RATE ADAPTATION AND MULTIPLEXING OF CONSTANT BIT RATE (CBR) CLIENT DATA FOR TRANSMISSION OVER A METRO TRANSPORT NETWORK (MTN)

    公开(公告)号:US20230006938A1

    公开(公告)日:2023-01-05

    申请号:US17745240

    申请日:2022-05-16

    Abstract: A system and method for performing rate adaptation and multiplexing of constant bit rate (CBR) client data for transmission over a Metro Transport Network (MTN) by defining a plurality of plurality of generic mapping procedure (GMP) thread frames for a respective stream of two or more streams of 64B/66B-encoded blocks of CR client data, defining a plurality of pseudo-Ethernet packets, mapping the plurality of GMP thread frames into consecutive pseudo-Ethernet packets, assembling a stream of GMP multiplexing frames comprising the consecutive pseudo-Ethernet packets, inserting a fixed number of idle blocks between the consecutive pseudo-Ethernet packets of the stream of GMP multiplexing frames and inserting an MTN path overhead (POH) frame into the stream of GMP multiplexing frames to generate a stream of GMP multiplexing rate adapted frames.

    Method for forming packaged semiconductor die with micro-cavity

    公开(公告)号:US11538726B2

    公开(公告)日:2022-12-27

    申请号:US17556790

    申请日:2021-12-20

    Abstract: A method for forming a packaged electronic die includes forming a plurality of bonding pads on a device wafer. A photoresist layer is deposited over the device wafer and is patterned so as to form a photoresist frame that completely surrounds a device formed on the device wafer. Conductive balls are deposited over the bonding pads. The wafer is cut to form the electronic die and the electronic die is placed over the substrate. The conductive balls are heated and compressed, moving the electronic die closer to the substrate such that the photoresist frame is in direct contact with the substrate or with a landing pad formed on the substrate. Encapsulant material is deposited such that the encapsulant material covers the electronic die and the substrate. The encapsulant material is cured so as to encapsulate the electronic die. The substrate is cut to separate the packaged electronic die.

    MEMORY ADDRESS PROTECTION
    148.
    发明申请

    公开(公告)号:US20220382629A1

    公开(公告)日:2022-12-01

    申请号:US17825352

    申请日:2022-05-26

    Abstract: A method for memory protection includes receiving a burst-write instruction that includes data and a burst-write address. The data are segmented into a plurality of data blocks. One or more bits of the burst-write address, or a hash of the burst-write address are concatenated to respective data blocks to obtain data-and-write-address-bit (DWAB) segments. A SECDED ECC is executed on respective DWAB segments to generate a corresponding plurality of sets of parity bits (DWAB-PB). Respective DWAB-PB are concatenated to the corresponding data block to generate corresponding forward-error-correction (FEC) blocks, none of the FEC blocks including the burst-write address or the hash of the burst-write address. A burst-write command and a respective portion of a respective FEC block is sent to respective memory devices during a plurality of beats until all of the beats of the burst-write have been sent.

    Method and apparatus for outlier management

    公开(公告)号:US11514994B1

    公开(公告)日:2022-11-29

    申请号:US17506735

    申请日:2021-10-21

    Abstract: A method for outlier management at a flash controller includes testing a flash memory device to identify one or more outlier blocks of the flash memory device. Hyperparameters for a DNN are loaded into a training circuit of the flash controller. Test reads of the one or more outlier blocks are performed and a number of errors in the test reads is identified. The DNN is trained using a mini-batch training process and using the identified number of errors in the test reads and is tested to determine whether the trained DNN meets a training error threshold. The performing, the identifying, the training and the testing are repeated until the trained DNN meets the training error threshold to identify parameters of an outlier-block DNN. A neural network operation is performed using the identified parameters to predict a set of TVSO values. A read is performed using the set of predicted TVSO values.

    Method and apparatus for reading a flash memory device

    公开(公告)号:US11514992B2

    公开(公告)日:2022-11-29

    申请号:US17234993

    申请日:2021-04-20

    Abstract: A method for reading a flash memory device includes storing configuration files of reliability-state Classification Neural Network (CNN) models and Regression Neural Network (RNN) inference models, and storing reliability-state tags corresponding to reliability states. The current number of P/E cycles is identified and a reliability-state CNN model is selected corresponding to the current number of P/E cycles. A neural network operation of the selected reliability-state CNN model is performed to identify a predicted reliability state. Corresponding reliability-state tags are identified and a corresponding RNN inference model is selected. A neural network operation of the selected RNN inference model is performed, using the reliability-state tags as input, to generate output indicating the shape of a threshold-voltage-shift read-error (TVS-RE) curve. Threshold Voltage Shift Offset (TVSO) values are identified corresponding to a minimum value of the TVS-RE curve and a read is performed using a threshold-voltage-shift read at the identified TVSO values.

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