公开(公告)号：US20130003805A1

公开(公告)日：2013-01-03

申请号：US13423585

申请日：2012-03-19

Applicant: Ni Zeng ,  Dasong Lin

Inventor： Ni Zeng ,  Dasong Lin

IPC: H04B17/00

CPC classification number: H04L25/0292

Abstract: A LIN receiver circuit includes filtering circuitry receiving an input signal and producing a filtered signal, a first comparator comparing the filtered signal to a threshold voltage, and a driver block producing the receiver output signal. The receiver circuit further includes an input comparator, signal-adjusting circuitry, and deglitching circuitry. The input comparator detects a low voltage on the input signal, and the signal-adjusting circuitry drives the filtered signal to a particular value to shorten the length of a glitch at the output of the first comparator. Meanwhile, the deglitching circuitry detects and removes the glitch to produce a deglitcher output signal. The deglitcher output signal is received by the driver block, which outputs the receiver output signal, wherein the receiver output signal contains no glitches, and is delayed by no more than 7.5 μs, thus providing immunity to ISO pulses.

Abstract translation: LIN接收器电路包括接收输入信号并产生滤波信号的滤波电路，将滤波后的信号与阈值电压进行比较的第一比较器和产生接收器输出信号的驱动器块。 接收器电路还包括输入比较器，信号调节电路和去角化电路。 输入比较器检测输入信号的低电压，并且信号调节电路将滤波后的信号驱动到特定值以缩短第一比较器输出端的毛刺长度。 同时，除冰电路检测并去除毛刺以产生脱色器输出信号。 输出信号由驱动器块接收，驱动器块输出接收器输出信号，其中接收器输出信号不含毛刺，并且延迟不大于7.5μs，从而提供对ISO脉冲的抗扰度。

公开(公告)号：US08344814B2

公开(公告)日：2013-01-01

申请号：US12975125

申请日：2010-12-21

Applicant: Henry Ge

Inventor： Henry Ge

IPC: H03L7/00 ,  H03B5/32 ,  G04B17/00

CPC classification number: H03L7/00 ,  H03L1/00

Abstract: A circuit comprises a frequency divider configured to receive an oscillating signal generated by an oscillator and to divide the oscillating signal into a clock signal, wherein the division ratio of the frequency divider is set to a value equal to one of: the integer part of the resonant frequency of the oscillator and the integer part of the resonant frequency of the oscillator plus 1. The circuit further comprises a control element which switchable connects or disconnects a calibration element to alter the frequency of the oscillation signal input to the frequency divider based on a number of oscillations that have transpired in the oscillating signal.

Abstract translation: 电路包括：分频器，被配置为接收由振荡器产生的振荡信号，并将振荡信号分频成时钟信号，其中分频器的分频比被设置为等于以下的一个值： 振荡器的谐振频率和振荡器的谐振频率的整数部分加1.电路还包括控制元件，其可切换地连接或断开校准元件，以改变输入到分频器的振荡信号的频率，基于 在振荡信号中发生的振荡数。

公开(公告)号：US20120286831A1

公开(公告)日：2012-11-15

申请号：US13556136

申请日：2012-07-23

Applicant: Henry Ge

Inventor： Henry Ge

IPC: H03K21/00

CPC classification number: H03L1/027 ,  H03L7/00

Abstract: A circuit comprises a frequency divider coupled to receive an oscillating signal generated by an oscillator and a division ratio and configured to divide the oscillating signal by the division ratio into a clock signal; a temperature compensation circuit configured to measure a temperature of the oscillator and generate a division ratio to be provided to the frequency divider and a first value on the basis of the measured temperature; and a control system configured to control connection between a calibration element and the oscillator based on the first value and the oscillating signal of the oscillator.

Abstract translation: 电路包括分频器，其耦合以接收由振荡器产生的振荡信号和分频比，并且被配置为将所述振荡信号除以所述分频比为时钟信号; 温度补偿电路，被配置为测量所述振荡器的温度，并且基于所测量的温度产生要提供给所述分频器的分频比和第一值; 以及控制系统，被配置为基于振荡器的第一值和振荡信号来控制校准元件与振荡器之间的连接。

公开(公告)号：US20120169323A1

公开(公告)日：2012-07-05

申请号：US13335762

申请日：2011-12-22

Applicant: Henry GE ,  Welsin WANG ,  Xing ZHANG

Inventor： Henry GE ,  Welsin WANG ,  Xing ZHANG

IPC: G01R19/00 ,  H02M7/06

CPC classification number: H02M7/06 ,  G01R11/40 ,  G01R11/42 ,  H02M7/068 ,  H02M2001/0064

Abstract: Congruent power and timing signals in a single electronic device. In an embodiment, a circuit may include just one isolation transformer operable to generate a power signal and a timing signal. On the secondary side, two branches may extract both a power signal and a clock signal for use in the circuit on the isolated secondary side. The first branch may be coupled to the transformer and operable to manipulate the signal into a power signal, such as a 5V DC signal. Likewise, the second circuit branch is operable to manipulate the signal into a clock signal, such as a 5 V signal with a frequency of 1 MHz. By extracting both a power supply signal and a clock signal from the same isolation transformer on the secondary side, valuable space may be saved on an integrated circuit device with only having a single winding for a single isolation transformer.

Abstract translation: 单个电子设备中的一致功率和定时信号。 在一个实施例中，电路可以仅包括一个可操作以产生功率信号和定时信号的隔离变压器。 在次级侧，两个分支可以提取功率信号和时钟信号，以在隔离次级侧的电路中使用。 第一分支可以耦合到变压器并且可操作以将信号操纵成诸如5V DC信号的功率信号。 类似地，第二电路支路可操作以将信号操纵成时钟信号，例如频率为1MHz的5V信号。 通过从次级侧的同一隔离变压器中提取电源信号和时钟信号，可以在集成电路设备上节省有价值的空间，只需要单个隔离变压器的绕组。

公开(公告)号：US20110156683A1

公开(公告)日：2011-06-30

申请号：US12925130

申请日：2010-10-14

Applicant: Hai Bo Zhang ,  Yan He

Inventor： Hai Bo Zhang ,  Yan He

IPC: G05F1/10

CPC classification number: H02M3/1582

Abstract: A current mode DC-DC controller operates with high efficiency even when the input and output voltages are close. Switches selectively connecting an input, ground and an output to inductor terminals are controlled in a buck/boost region to alternate between operation as a buck converter and operation as a boost converter. The number of switches repeatedly changing state is thus reduced, lowering switching losses and improving conversion efficiency. Current through the inductor during operation is sensed and compared to an error value to control switching from buck mode operation to boost mode operation and back.

Abstract translation: 即使输入和输出电压接近，电流模式DC-DC控制器也能以高效率运行。 选择性地将输入，接地和输出连接到电感器端子的开关在降压/升压区域中被控制，以在作为降压转换器的操作和作为升压转换器的操作之间交替。 因此，重复改变状态的开关数量减少，降低开关损耗并提高转换效率。 在运行期间通过电感器的电流被感测并与误差值进行比较，以控制从降压模式操作到升压模式操作和返回的切换。

公开(公告)号：US20110156676A1

公开(公告)日：2011-06-30

申请号：US12859478

申请日：2010-08-19

Applicant: Liang ZHU ,  Jun LIU ,  Hai Bo ZHANG

Inventor： Liang ZHU ,  Jun LIU ,  Hai Bo ZHANG

IPC: G05F1/10

CPC classification number: G05F1/575

Abstract: An embodiment of a method includes generating a regulated output signal from a regulated intermediate signal in response to a reference signal and the regulated output signal, and generating the regulated intermediate signal from an input signal in response to the regulated output signal and the regulated intermediate signal. By generating one regulated signal (e.g., a regulated output voltage) from another regulated signal (e.g., a regulated intermediate voltage), one may significantly reduce the magnitude of the ripple component of the one regulated signal as compared to a conventional regulation technique. Furthermore, by generating the regulated intermediate signal in response to the regulated output signal, one may significantly increase the efficiency of the regulation as compared to conventional signal regulation.

Abstract translation: 一种方法的实施例包括响应于参考信号和调节的输出信号从调节的中间信号产生调节的输出信号，以及响应于调节的输出信号和调节的中间信号从输入信号产生调节的中间信号 。 通过从另一个调节信号（例如，调节的中间电压）产生一个调节信号（例如，稳定的输出电压），与传统的调节技术相比，可以显着地减小一个调节信号的纹波分量的幅度。 此外，通过响应于调节的输出信号产生调节的中间信号，与传统的信号调节相比，可以显着提高调节的效率。

公开(公告)号：US20110074481A1

公开(公告)日：2011-03-31

申请号：US12821883

申请日：2010-06-23

Applicant: Hong Wu Lin

Inventor： Hong Wu Lin

IPC: H03K3/02

CPC classification number: H02M3/07 ,  H02M2003/071

Abstract: A charge pump circuit includes a first power transistor selectively actuated by a first control signal to deliver relatively higher amounts of current to a capacitor and a second non-power transistor connected in parallel with the first power transistor and selectively actuated by a second control signal to deliver relatively lower amounts of current to the capacitor. The charge pump circuit includes a pumped voltage output that is sensed to generate a sensed voltage output. A comparison circuit compares the sensed voltage output to a threshold voltage. A logic circuit receives an output of the comparison circuit and enables the first power transistor and disables the second non-power transistor in a first mode of operation if the comparison is not satisfied. The logic circuit further disables the first power transistor and enables the second non-power transistor in a second mode of operation if the comparison is satisfied. The logic circuit returns from the second mode of operation to the first mode of operation after the comparison is subsequently not satisfied.

Abstract translation: 电荷泵电路包括由第一控制信号选择性地驱动的第一功率晶体管，以向电容器提供相对较大量的电流，以及与第一功率晶体管并联连接并由第二控制信号选择性地驱动的第二非功率晶体管， 向电容器提供相对较低的电流量。 电荷泵电路包括被感测以产生感测电压输出的泵浦电压输出。 比较电路将检测到的电压输出与阈值电压进行比较。 逻辑电路接收比较电路的输出，并使得第一功率晶体管能够在第一操作模式中禁用第二非功率晶体管，如果不满足比较。 如果满足比较，则逻辑电路进一步禁用第一功率晶体管并使第二非功率晶体管处于第二操作模式。 在比较不满足后，逻辑电路从第二操作模式返回到第一操作模式。

公开(公告)号：US20100123508A1

公开(公告)日：2010-05-20

申请号：US12578572

申请日：2009-10-13

Applicant: Gang Zha ,  Guenter Neidhardt ,  Peter Kirchlechner

Inventor： Gang Zha ,  Guenter Neidhardt ,  Peter Kirchlechner

IPC: H03K17/00

CPC classification number: H03K17/005 ,  H03K17/16

Abstract: A first switching circuit has an input for receiving a first input signal, and a second switching circuit has an input for receiving a second input signal. A node is connected to receive outputs from both the first and second switching circuits. A filter receives an unfiltered signal from the node to generate an output signal. A circuit is provided to alternately actuate the first and second switching circuits during a transition time period so as to smoothly transition the output of the filter between the first and second input signals. At least one of the first and second input signals is a time-varying analog signal. The smooth transition between the first and second input signals has a shape determined by pulse width and frequency characteristics of pulses output by the circuit to alternately actuate the first and second switching circuits. The shape may include a linear ramp, an S-shaped curve, a parabolic curve and a hyperbolic curve.

Abstract translation: 第一开关电路具有用于接收第一输入信号的输入端，第二开关电路具有用于接收第二输入信号的输入端。 连接节点以接收来自第一和第二开关电路的输出。 滤波器从节点接收未滤波的信号以产生输出信号。 提供电路以在转变时间周期期间交替地致动第一和第二开关电路，以便在第一和第二输入信号之间平滑地转换滤波器的输出。 第一和第二输入信号中的至少一个是时变模拟信号。 第一和第二输入信号之间的平滑过渡具有由电路输出的脉冲的脉冲宽度和频率特性确定的形状，以交替地致动第一和第二开关电路。 该形状可以包括线性斜坡，S形曲线，抛物线曲线和双曲线。

公开(公告)号：US20090322428A1

公开(公告)日：2009-12-31

申请号：US12473131

申请日：2009-05-27

Applicant: Kunkun Zheng ,  Jianhua Zhao

Inventor： Kunkun Zheng ,  Jianhua Zhao

IPC: H03F3/45

CPC classification number: H03F3/45098 ,  H03F2203/45356 ,  H03F2203/45484 ,  H03F2203/45492 ,  H03F2203/45506 ,  H03F2203/45648 ,  H03F2203/45682

Abstract: A tunable, linear operational transconductance amplifier includes a differential voltage to current conversion unit adapted to generate first and second output signals at respective first and second output nodes responsive to first and second differential input signals. A first current amplification unit is adapted to generate a third output signal responsive to the first output signal and first and second control signals. A second current amplification unit is adapted to generate a fourth output signal responsive to the second output signal and the first and second control signals.

Abstract translation: 可调谐线性运算跨导放大器包括差分电压到电流转换单元，其适于响应于第一和第二差分输入信号在相应的第一和第二输出节点产生第一和第二输出信号。 第一电流放大单元适于响应于第一输出信号和第一和第二控制信号产生第三输出信号。 第二电流放大单元适于响应于第二输出信号和第一和第二控制信号产生第四输出信号。

公开(公告)号：US12231102B2

公开(公告)日：2025-02-18

申请号：US18493282

申请日：2023-10-24

Applicant: STMicroelectronics (Shenzhen) R&D Co., Ltd.

Inventor： XiangSheng Li ,  Ru Feng Du

IPC: H03G3/30 ,  H03F3/187 ,  H04R3/00 ,  H04R29/00

Abstract: An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.