公开(公告)号：US07970982B2

公开(公告)日：2011-06-28

申请号：US11761620

申请日：2007-06-12

Applicant: Ki-Hong Kim ,  Byeong-Hoon Lee ,  Seung-Won Lee ,  Sun-Kwon Kim

Inventor： Ki-Hong Kim ,  Byeong-Hoon Lee ,  Seung-Won Lee ,  Sun-Kwon Kim

IPC: G06F12/02

CPC classification number: G11C16/20

Abstract: A memory card includes: a first memory chip responding to all commands input externally; and a second memory chip responding to commands, among the commands input externally, relevant to reading, programming, and erasing operations with data. Card identification information stored in the first memory chip includes capacity information corresponding to a sum of sizes of the first and second memory chips. The plurality of memory chips of the memory card are useful in designing the memory card with storage capacity in various forms.

Abstract translation: 存储卡包括：响应于外部输入的所有命令的第一存储器芯片; 以及响应命令的第二存储器芯片，在外部输入的命令中与数据的读取，编程和擦除操作相关。 存储在第一存储器芯片中的卡识别信息包括对应于第一和第二存储器芯片的尺寸之和的容量信息。 存储卡的多个存储芯片可用于以各种形式设计具有存储容量的存储卡。

公开(公告)号：US20100281489A1

公开(公告)日：2010-11-04

申请号：US12662657

申请日：2010-04-27

Applicant: Seung Won Lee ,  Shi Hwa Lee ,  Dong-In Kang ,  Mikyung Kang

Inventor： Seung Won Lee ,  Shi Hwa Lee ,  Dong-In Kang ,  Mikyung Kang

IPC: G06F9/46

CPC classification number: G06F9/50 ,  G06F9/5038 ,  G06F9/5066 ,  G06F2209/5017

Abstract: Provided is a method and system for dynamically parallelizing an application program. Specifically, provided is a method and system having multi-core control that may verify a number of available threads according to an application program and dynamically parallelize data based on the verified number of available threads. The method and system for dynamically parallelizing the application program may divide a data block to be processed according to the application program based on a relevant data characteristic and dynamically map the threads to division blocks, and thereby enhance a system performance.

Abstract translation: 提供了一种用于动态并行化应用程序的方法和系统。 特别地，提供了一种具有多核控制的方法和系统，其可以根据应用程序验证多个可用线程，并且基于经验证的可用线程数动态地并行化数据。 用于动态并行化应用程序的方法和系统可以基于相关数据特征，根据应用程序划分要处理的数据块，并将线程动态地映射到划分块，从而提高系统性能。

公开(公告)号：US07750611B2

公开(公告)日：2010-07-06

申请号：US11951594

申请日：2007-12-06

Applicant: Seung-Won Lee

Inventor： Seung-Won Lee

IPC: G05F1/563 ,  G05F1/565

CPC classification number: G05F1/56

Abstract: A voltage controller may include a pulse generator and an internal voltage control circuit coupled to the pulse generator. The pulse generator may be configured to generate a control signal in response to at least one of a mode signal and/or an external voltage. The internal voltage control circuit may be configured to generate an internal voltage at an internal voltage node, and the internal voltage control circuit may include a voltage divider, first and second comparators, and a driver. The voltage divider may be coupled between the internal voltage node and a first reference voltage, and the voltage divider may generate a feedback voltage that is between the internal voltage and the first reference voltage. The first comparator may be configured to generate a first comparison result responsive to comparing the feedback voltage with a second reference voltage, and the second comparator may be configured to generate a second comparison result responsive to comparing the feedback voltage with the second reference voltage in response to the control signal. The driver may be coupled between an external voltage and the internal voltage node, and the driver may be configured to generate the internal voltage responsive to the first and second comparison results. Related methods and smart cards are also discussed.

Abstract translation: 电压控制器可以包括脉冲发生器和耦合到脉冲发生器的内部电压控制电路。 脉冲发生器可以被配置为响应于模式信号和/或外部电压中的至少一个而产生控制信号。 内部电压控制电路可以被配置为在内部电压节点处产生内部电压，并且内部电压控制电路可以包括分压器，第一和第二比较器以及驱动器。 分压器可以耦合在内部电压节点和第一参考电压之间，并且分压器可以产生处于内部电压和第一参考电压之间的反馈电压。 第一比较器可以被配置为响应于将反馈电压与第二参考电压进行比较而产生第一比较结果，并且第二比较器可以被配置为响应于响应于将反馈电压与响应于第二参考电压进行比较而产生第二比较结果 到控制信号。 驱动器可以耦合在外部电压和内部电压节点之间，并且驱动器可以被配置为响应于第一和第二比较结果而产生内部电压。 还讨论了相关方法和智能卡。

公开(公告)号：US07669788B2

公开(公告)日：2010-03-02

申请号：US10864994

申请日：2004-06-10

Applicant: Yong-Seok Park ,  Kyoung-Heon Heo ,  Seung-Won Lee

Inventor： Yong-Seok Park ,  Kyoung-Heon Heo ,  Seung-Won Lee

IPC: B05B1/26

CPC classification number: B05C5/0254 ,  B05B13/0207

Abstract: A fluid injector for treating a surface of a flat display panel includes a case provided with a cavity for receiving fluid; a pair of nozzle guiders coupled to the case and disposed facing each other; a gap-adjusting plate disposed between the nozzle guiders to adjust a gap between the nozzle guiders; and a coupling device for coupling the nozzle guiders to the gap-adjusting plate.

Abstract translation: 用于处理平面显示面板的表面的流体注入器包括设置有用于接收流体的空腔的壳体; 一对连接到壳体并相对设置的喷嘴引导器; 设置在所述喷嘴引导件之间的间隙调节板，以调节所述喷嘴引导件之间的间隙; 以及用于将喷嘴引导件联接到间隙调节板的联接装置。

公开(公告)号：US20090187912A1

公开(公告)日：2009-07-23

申请号：US12216149

申请日：2008-06-30

Applicant: Seung-won Lee

Inventor： Seung-won Lee

IPC: G06F9/46

CPC classification number: G06F9/4856 ,  Y02D10/24 ,  Y02D10/32

Abstract: A method and apparatus for migrating a task in a multi-processor system. The method includes examining whether a second process has been allocated to a second processor, the second process having a same instruction to execute as a first process and having different data to process in response to the instruction from the first process, the instruction being to execute the task; selecting a method of migrating the first process or a method of migrating a thread included in the first process based on the examining and migrating the task from a first processor to the second processor using the selected method. Therefore, cost and power required for task migration can be minimized. Consequently, power consumption can be maintained in a low-power environment, such as an embedded system, which, in turn, optimizes the performance of the multi-processor system and prevents physical damage to the circuit of the multi-processor system.

Abstract translation: 一种用于在多处理器系统中迁移任务的方法和装置。 该方法包括检查第二处理是否已被分配给第二处理器，第二处理具有作为第一处理执行的相同指令，并且具有响应于来自第一处理的指令而处理的不同数据，该指令将执行 任务; 基于使用所选择的方法从第一处理器检查和迁移任务到第二处理器，选择迁移第一进程的方法或迁移包括在第一进程中的线程的方法。 因此，任务迁移所需的成本和功耗可以最小化。 因此，能够在诸如嵌入式系统的低功率环境中维持功率消耗，这进而优化多处理器系统的性能并防止对多处理器系统的电路的物理损坏。

公开(公告)号：US20090091739A1

公开(公告)日：2009-04-09

申请号：US12202645

申请日：2008-09-02

Applicant: Hong Ki KIM ,  Chan Yong Park ,  Seung Won Lee ,  Sun Ki Min

Inventor： Hong Ki KIM ,  Chan Yong Park ,  Seung Won Lee ,  Sun Ki Min

IPC: G01C3/08

CPC classification number: G01B11/026 ,  G01S7/497 ,  G01S17/10

Abstract: A laser measuring device maintains high responsivity irrespective of changes in surrounding environment, provides more correct measurement and long distance measurement due to reduced noise, and ensures the safety and reliability of a product. A first light emitter emits first wavelength light having a first wavelength. A second light emitter emits second wavelength light having a second wavelength, the second light emitter being arranged perpendicular to the first light emitter. An optical mirror allows one of the first wavelength light and the second wavelength light to pass but reflecting the other one. A first band pass filter for allows the first wavelength light to pass. A second band pass filter allows the second wavelength light to pass. A light receiver receives incident light, which arrives through one of the first and second band pass filters. A controller activates at least one of the first and second light emitters.

Abstract translation: 激光测量装置保持高响应度，不管周围环境如何变化，由于噪音降低，可提供更准确的测量和长距离测量，并确保产品的安全性和可靠性。 第一发光器发射具有第一波长的第一波长光。 第二发光体发射具有第二波长的第二波长光，第二光发射器垂直于第一光发射器布置。 光学镜允许第一波长光和第二波长光中的一个通过但反射另一个。 用于允许第一波长光通过的第一带通滤波器。 第二带通滤波器允许第二波长光通过。 光接收器接收通过第一和第二带通滤波器之一到达的入射光。 控制器激活第一和第二发光体中的至少一个。

公开(公告)号：US07499322B2

公开(公告)日：2009-03-03

申请号：US11734082

申请日：2007-04-11

Applicant: Seung Won Lee ,  Ki Hong Kim ,  Sun Kwon Kim ,  Byeong Hoon Lee

Inventor： Seung Won Lee ,  Ki Hong Kim ,  Sun Kwon Kim ,  Byeong Hoon Lee

IPC: G11C16/04

CPC classification number: G11C11/412 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C2207/002

Abstract: An integrated circuit memory system includes an integrated circuit device having a random access memory array, a non-volatile memory array (e.g., flash memory array) and a data transfer circuit therein. The memory arrays and data transfer circuit may be included in a common integrated circuit chip. The random access memory (RAM) array includes a plurality of columns of RAM cells and a first plurality of bit lines, which are electrically connected to the plurality of columns of RAM cells. The non-volatile memory array includes a plurality of columns of non-volatile memory cells and a second plurality of bit lines, which are electrically connected to a plurality of columns of non-volatile memory cells. The data transfer circuit is electrically connected to the first and second pluralities of bit lines. The data transfer circuit is configured to support direct bidirectional communication between the first and second pluralities of bit lines.

Abstract translation: 集成电路存储器系统包括具有随机存取存储器阵列，非易失性存储器阵列（例如闪存阵列）和其中的数据传输电路的集成电路器件。 存储器阵列和数据传输电路可以包括在公共集成电路芯片中。 随机存取存储器（RAM）阵列包括多个RAM单元列和第一多个位线，它们电连接到多个RAM单元列。 非易失性存储器阵列包括多列非易失性存储器单元和第二多个位线，其电连接到多列非易失性存储器单元。 数据传输电路电连接到第一和第二多个位线。 数据传输电路被配置为支持第一和第二多个位线之间的直接双向通信。

公开(公告)号：US20080195916A1

公开(公告)日：2008-08-14

申请号：US12010244

申请日：2008-01-23

Applicant: Seung-won Lee ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

Inventor： Seung-won Lee ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

IPC: G11C29/00

CPC classification number: G11C16/3431 ,  G06F11/1068 ,  G11C16/3418 ,  G11C2029/0411

Abstract: Example embodiments provide a method and apparatus of correcting error data due to charge loss within a non-volatile memory device including a plurality of memory cells. The method of correcting error data within the non-volatile memory devices may include detecting error data in a second data group by comparing a first data group read from memory cells in response to a first voltage with the second data group read from memory cells in response to a second voltage. The second voltage is higher than the first voltage. Error data in the first data group is detected by error-correcting code (ECC). Re-writing data in the memory cells is performed by correcting error data in the first data group and error data in the second data group. A central processing unit (CPU) may detect error in the second data group. The second data group may be read through a page buffer and compared with the first data group stored in a SRAM. The detected error may be updated to the page buffer. Error data in the first data group may be updated to the page buffer. The CPU corrects error in the final error data, and the page buffer rewrites the corrected data in the plurality of memory cells.

Abstract translation: 示例性实施例提供了一种在包括多个存储器单元的非易失性存储器件内由于电荷损失而校正误差数据的方法和装置。 校正非易失性存储器件中的错误数据的方法可以包括通过将响应于第一电压的存储器单元读取的第一数据组与从存储器单元读取的第二数据组进行响应来检测第二数据组中的错误数据 到第二电压。 第二电压高于第一电压。 通过纠错码（ECC）检测第一数据组中的错误数据。 通过对第一数据组中的错误数据和第二数据组中的错误数据进行校正，来重新写入存储器单元中的数据。 中央处理单元（CPU）可以检测第二数据组中的错误。 可以通过页缓冲器读取第二数据组，并与存储在SRAM中的第一数据组进行比较。 检测到的错误可能更新到页面缓冲区。 第一个数据组中的错误数据可能更新到页面缓冲区。 CPU更正最终错误数据中的错误，并且页缓冲区重写多个存储单元中的校正数据。

公开(公告)号：US20080183954A1

公开(公告)日：2008-07-31

申请号：US12016680

申请日：2008-01-18

Applicant: Seung-won LEE ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

Inventor： Seung-won LEE ,  Byeong-hoon Lee ,  Ki-hong Kim ,  Sun-kwon Kim

IPC: G06F12/02

CPC classification number: G06F13/4239

Abstract: An apparatus and method for controlling an embedded NAND flash memory. The apparatus includes a code memory storing code information for controlling an access to a NAND flash memory. A register stores code information corresponding to a command to be executed by the NAND flash memory. A central processing unit (CPU) reads the code information corresponding to the command to be executed by the NAND flash memory from the code memory and stores the read code information in the register. A hard-wired logic circuit performs the NAND flash memory access according to the code information stored in the register.

Abstract translation: 一种用于控制嵌入式NAND闪速存储器的装置和方法。 该装置包括存储用于控制对NAND快闪存储器的访问的代码信息的代码存储器。 寄存器存储与由NAND闪存执行的命令对应的代码信息。 中央处理单元（CPU）从代码存储器读取与NAND闪存要执行的命令对应的代码信息，并将读取的代码信息存储在寄存器中。 硬接线逻辑电路根据存储在寄存器中的代码信息执行NAND闪速存取存取。

公开(公告)号：US20080168210A1

公开(公告)日：2008-07-10

申请号：US12004068

申请日：2007-12-20

Applicant: Jae-don Lee ,  Seung-won Lee ,  Jeong-joon Yoo ,  Young-sam Shin ,  Min-kyu Jeong ,  Keun-soo Yim

Inventor： Jae-don Lee ,  Seung-won Lee ,  Jeong-joon Yoo ,  Young-sam Shin ,  Min-kyu Jeong ,  Keun-soo Yim

IPC: G06F12/00

CPC classification number: G06F11/1008

Abstract: A method and apparatus for managing a memory are provided. It is possible to rapidly recover the area allocated or desired to be returned by easily recognizing a range of the area allocated or desired to be returned over the entire area of the memory by recognizing an original area of a predetermined memory chunk interrupted by a neighboring memory chunk among a series of memory chunks that make up the memory by considering an original area of the neighboring memory chunk and by recovering the predetermined memory chunk and the recognized area to their original areas, when the area allocated to or returned by an application program is interrupted.

Abstract translation: 提供了一种用于管理存储器的方法和装置。 通过识别由相邻存储器中断的预定存储器块的原始区域，可以容易地识别在存储器的整个区域中分配或期望返回的区域的范围，来快速恢复分配或期望返回的区域 在通过考虑相邻存储块的原始区域构成存储器的一系列存储块中的块，并且通过将分配给应用程序或由应用程序返回的区域归为原始区域时将预定的存储块和识别的区域恢复到其原始区域 中断了