Abstract:
A driver IC device includes a correction function having a unit-block setting unit for dividing pixels of a display panel into preset units so as to set the same as a plurality of unit-blocks; a correction route (LUT) setting unit for setting a LUT having a plurality of sub-regions arranged in the same form in response to an arrangement of the pixels included in the unit-blocks set through the unit-block setting unit; a storage unit for storing the LUT set through the LUT setting unit, and storing respective gain values and offset values for the plurality of unit-blocks set through the unit-block setting unit; a changing unit for changing an input value (input gray) inputted to the pixels of the display panel, by using the gain values and offset values stored in the storage unit; and a correction output unit for generating a correction output value (output gray) of the pixels in the unit-blocks of the display panel by using a change value obtained through the changing unit and a coordinate value of the LUT set through the LUT setting unit.
Abstract:
Provided is a method and apparatus for preventing a stack overflow in an embedded system. The method of preventing a stack overflow includes: reading a maximum stack usage of at least one function for executing a requested operation from maximum stack usages of functions provided from a kernel, which are stored in advance; and processing the requested operation on the basis of the read maximum stack usage of the at least one function and a size of a usable region in a stack for the requested operation. Accordingly, the stack overflow can be prevented without generating a run-time overhead.
Abstract:
Memory mapping in small units using a segment and subsegments is described, and thus it is possible to control a memory access even using a small amount of hardware, and it is possible to reduce costs incurred by hardware. Additionally, it is possible to prevent a memory from being destroyed due to a task error in the multi-processor system.
Abstract:
A scheduling method, medium and apparatus are provided. In the scheduling method, medium and apparatus, it is possible to prevent the possibility that the order between the priorities of the tasks represented by the expired timers and the tasks requested by the interrupt is reversed while also not deteriorating the performance of a real time operating system (RTOS), even though the number of timers expired when the interrupt occurs or that are already expired before the interrupt occurs is large, by selecting a timer for representing a point of time corresponding to a point of time when an interrupt occurs from among one or more timers each of which representing a task, a point of time assigned to the tasks, and a priority assigned to the task and executing a task represented by the selected timer and one or more tasks requested by the interrupt in order of priority.
Abstract:
A synchronization scheduling apparatus and method in a real-time multi-core system are described. The synchronization scheduling apparatus may include a plurality of cores, each having at least one wait queue, a storage unit to store information regarding a first core receiving a wake-up signal in a previous cycle among the plurality of cores, and a scheduling processor to schedule tasks stored in the at least one wait queue, based on the information regarding the first core.
Abstract:
A smart card includes an internal voltage generator, a clock generator, and an internal circuit. The internal voltage generator generates a first internal voltage and a second internal voltage based on an input voltage received through an antenna. A level of the second internal voltage is lower than a level of the first internal voltage. The clock generator receives the first internal voltage and the second internal voltage to generate a clock signal. A frequency of the clock signal is changed according to the level of the first internal voltage. The internal circuit operates based on the clock signal and the second internal voltage.
Abstract:
A memory system includes a memory and a memory controller operating to control the memory. The memory includes a random accessible memory including a memory cell array operable in a random access mode, a NAND flash memory, and a selection circuit making the memory controller operate either one of the random accessible memory or the NAND flash memory.
Abstract:
The present invention relates to a diagnostic method for acute myeloid leukemia, in particular, a method for using CFH or ApoH in patient sera as biochemical diagnostic markers to determine complete remission in acute myeloid leukemia. In accordance with this invention, CFH and ApoH are identified as a novel biochemical marker for understanding the biological mechanism and responsiveness to disease in AML patients after induction chemotherapy, and can be used as a biochemical marker for evaluating the prognosis of disease in patients after induction chemotherapy.
Abstract:
A method for preparing a cathode active material for a lithium secondary battery is provided. The preparing method includes: adding a phosphorus compound to a transition metal oxide dispersion liquid to prepare a coating liquid; drying the coating liquid to prepare a powder including phosphorus oxide coated on the surface of the transition metal oxide; and dry-mixing the powder coated with the phosphorus oxide with a lithium intercalation compound, and then firing the mixture to form a solid solution compound of L1-M1-M2-P—O (where M1 is a transition metal derived from transition metal oxide, and M2 is a metal derived from lithium intercalation compound) on the surface of the lithium intercalation compound. The method for preparing a cathode active material for a lithium secondary battery simplifies the conventional preparing process to save process cost, and it provides comparable electrochemical characteristics to a cathode active material obtained from a wet process.
Abstract:
A virtual architecture generating apparatus and method, a runtime system, a multi-core system, and methods of operating the runtime system and the multi-core system may include analyzing a requirement of an application, a feature of the application, and a requirement of a system enabling an execution of the application, and include generating a virtual architecture corresponding to the application, based on a physical architecture of a reconfigurable processor, the analyzed requirements and the analyzed feature.