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公开(公告)号：US09448844B2
公开(公告)日：2016-09-20
申请号：US12881752
申请日：2010-09-14
Applicant: Jae Don Lee , Shi Hwa Lee , Seung Won Lee , Chae Seok Lim , Min Kyu Jeong
Inventor： Jae Don Lee , Shi Hwa Lee , Seung Won Lee , Chae Seok Lim , Min Kyu Jeong
CPC classification number: G06F9/5016
Abstract: Provided is a computing system having a hierarchical memory structure. When a data structure is allocated with respect to a task processed in the computing system, the data structure is divided and a portion of the data structure is allocated to a high speed memory of the hierarchical memory structure and a remaining data structure is allocated to a low speed memory of the hierarchical memory.
Abstract translation: 提供了具有分层存储器结构的计算系统。 当相对于在计算系统中处理的任务分配数据结构时，数据结构被划分，并且数据结构的一部分被分配给分层存储器结构的高速存储器，并且剩余的数据结构被分配给 分层存储器的低速存储器。
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2.发明授权Real-time scheduling of task sets and determination of task sets based on verified weight, cache hit radio of the tasks and available processing cores 有权基于验证权重，任务的高速缓存命中率和可用处理核心，任务集的实时调度和任务集的确定公开(公告)号：US08782649B2
公开(公告)日：2014-07-15
申请号：US12453171
申请日：2009-04-30
Applicant: Min Kyu Jeong
Inventor： Min Kyu Jeong
IPC: G06F9/46
CPC classification number: G06F9/4881 , G06F2209/483 , G06F2209/5017
Abstract: A central processing unit (CPU) and a real-time scheduling method applicable in the CPU are disclosed. The CPU may determine a first task set and a second task set from among assigned tasks, schedule the determined first task set in a single core to enable the task to be processed, and schedule the determined second task set in a multi-core to enable the task to be processed.
Abstract translation: 公开了一种适用于CPU的中央处理单元（CPU）和实时调度方法。 CPU可以从分配的任务中确定第一任务集和第二任务集，在单个核中调度所确定的第一任务集以使得能够处理任务，并且在多核中调度所确定的第二任务集以使能 要处理的任务。
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公开(公告)号：US08194658B2
公开(公告)日：2012-06-05
申请号：US11979737
申请日：2007-11-07
Applicant: Young-sam Shin , Seung-won Lee , Han-cheol Kim , Jeong-joon Yoo , Jae-don Lee , Min-kyu Jeong , Keun-soo Yim
Inventor： Young-sam Shin , Seung-won Lee , Han-cheol Kim , Jeong-joon Yoo , Jae-don Lee , Min-kyu Jeong , Keun-soo Yim
IPC: H04L12/56
CPC classification number: H04L47/564 , H04L47/19 , H04L47/24 , H04L47/50
Abstract: A method and apparatus transmitting and receiving in a real-time system are disclosed. The method of transmitting in a real-time system includes scheduling a task included in a socket based on a predetermined transmission option designated to the socket, and transmitting a packet generated by the scheduled task based on the predetermined transmission option, so that real-time communications of a network communication can be secured and resources of the system can be efficiently used, thereby, transmitting and receiving data according to the required characteristics of transmission and reception.
Abstract translation: 公开了一种在实时系统中发送和接收的方法和装置。 在实时系统中发送的方法包括基于指定给套接字的预定传输选项来调度包含在套接字中的任务，以及基于预定传输选项发送由调度任务生成的分组，使得实时 可以确保网络通信的通信，并且可以有效地利用系统的资源，从而根据所需的发送和接收特性发送和接收数据。
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公开(公告)号：US20080168210A1
公开(公告)日：2008-07-10
申请号：US12004068
申请日：2007-12-20
Applicant: Jae-don Lee , Seung-won Lee , Jeong-joon Yoo , Young-sam Shin , Min-kyu Jeong , Keun-soo Yim
Inventor： Jae-don Lee , Seung-won Lee , Jeong-joon Yoo , Young-sam Shin , Min-kyu Jeong , Keun-soo Yim
IPC: G06F12/00
CPC classification number: G06F11/1008
Abstract: A method and apparatus for managing a memory are provided. It is possible to rapidly recover the area allocated or desired to be returned by easily recognizing a range of the area allocated or desired to be returned over the entire area of the memory by recognizing an original area of a predetermined memory chunk interrupted by a neighboring memory chunk among a series of memory chunks that make up the memory by considering an original area of the neighboring memory chunk and by recovering the predetermined memory chunk and the recognized area to their original areas, when the area allocated to or returned by an application program is interrupted.
Abstract translation: 提供了一种用于管理存储器的方法和装置。 通过识别由相邻存储器中断的预定存储器块的原始区域，可以容易地识别在存储器的整个区域中分配或期望返回的区域的范围，来快速恢复分配或期望返回的区域 在通过考虑相邻存储块的原始区域构成存储器的一系列存储块中的块，并且通过将分配给应用程序或由应用程序返回的区域归为原始区域时将预定的存储块和识别的区域恢复到其原始区域 中断了
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公开(公告)号：US09152547B2
公开(公告)日：2015-10-06
申请号：US12591946
申请日：2009-12-04
Applicant: Jae Don Lee , Shi Hwa Lee , Seung Won Lee , Chae Seok Im , Min Kyu Jeong
Inventor： Jae Don Lee , Shi Hwa Lee , Seung Won Lee , Chae Seok Im , Min Kyu Jeong
IPC: G06F12/02
CPC classification number: G06F12/023 , G06F12/0292
Abstract: Disclosed is a scratch pad memory management device and a method thereof. The scratch pad memory management device divides a scratch pad memory into a plurality of unit blocks, maintains a memory allocation table corresponding to indices of the plurality of unit blocks in a main memory, and manages the scratch pad memory.
Abstract translation: 公开了一种便笺本式存储器管理装置及其方法。 临时存储器管理装置将暂存器存储器划分为多个单位块，维持与主存储器中的多个单位块的索引相对应的存储器分配表，并管理暂存存储器。
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Patent Agency Ranking
6.发明授权Hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization 有权硬件加速装置，方法和计算机可读介质有效地处理多核同步公开(公告)号：US08688885B2
公开(公告)日：2014-04-01
申请号：US12904782
申请日：2010-10-14
Applicant: Chae Seok Im , Shi Hwa Lee , Seung Won Lee , Jae Don Lee , Min Kyu Jeong
Inventor： Chae Seok Im , Shi Hwa Lee , Seung Won Lee , Jae Don Lee , Min Kyu Jeong
CPC classification number: G06F1/3203 , G06F1/3287 , Y02D10/171
Abstract: Provided is a hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization. A processor core that fails to acquire a lock variable may be switched to a low power sleep mode and a waste of power may be reduced. Additionally, when a lock variable is returned, a wakeup signal may be transmitted to a processor core operated in the low power sleep mode, and the processor core may be activated.
Abstract translation: 提供了一种有效处理多核同步的硬件加速装置，方法和计算机可读介质。 不能获取锁定变量的处理器核心可以切换到低功率睡眠模式，并且可能减少功率的浪费。 此外，当返回锁定变量时，可以将唤醒信号发送到以低功率睡眠模式操作的处理器核心，并且可以激活处理器核心。
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7.发明申请Computing system, method and computer-readable medium processing debug information in computing system 有权计算系统中的计算系统，方法和计算机可读介质处理调试信息公开(公告)号：US20110119656A1
公开(公告)日：2011-05-19
申请号：US12923869
申请日：2010-10-12
Applicant: Jae Don Lee , Shi Hwa Lee , Seung Won Lee , Chae Seok Im , Min Kyu Jeong
Inventor： Jae Don Lee , Shi Hwa Lee , Seung Won Lee , Chae Seok Im , Min Kyu Jeong
IPC: G06F9/44
CPC classification number: G06F11/0703 , G06F11/0736 , G06F11/366 , G06F11/3664
Abstract: Disclosed are a system, method and computer-readable medium related to processing debug information from an embedded system. Source code of an application program to be used in an embedded system may be compiled by a computing system. The application program may include a debug code line. A minimum amount of debug information is stored in an embedded system, reducing memory overhead and waste of clock cycles of a processor.
Abstract translation: 公开了一种与从嵌入式系统处理调试信息相关的系统，方法和计算机可读介质。 在嵌入式系统中使用的应用程序的源代码可以由计算系统编译。 应用程序可以包括调试代码行。 最少量的调试信息存储在嵌入式系统中，减少了内存开销并浪费了处理器的时钟周期。
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8.发明申请公开(公告)号：US20110252258A1
公开(公告)日：2011-10-13
申请号：US12904782
申请日：2010-10-14
Applicant: Chae Seok IM , Shi Hwa LEE , Seung Won LEE , Jae Don LEE , Min Kyu JEONG
Inventor： Chae Seok IM , Shi Hwa LEE , Seung Won LEE , Jae Don LEE , Min Kyu JEONG
CPC classification number: G06F1/3203 , G06F1/3287 , Y02D10/171
Abstract: Provided is a hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization. A processor core that fails to acquire a lock variable may be switched to a low power sleep mode and a waste of power may be reduced. Additionally, when a lock variable is returned, a wakeup signal may be transmitted to a processor core operated in the low power sleep mode, and the processor core may be activated.
Abstract translation: 提供了一种有效处理多核同步的硬件加速装置，方法和计算机可读介质。 不能获取锁定变量的处理器核心可以切换到低功率睡眠模式，并且可能减少功率的浪费。 此外，当返回锁定变量时，可以将唤醒信号发送到以低功率睡眠模式操作的处理器核心，并且可以激活处理器核心。
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公开(公告)号：US07996630B2
公开(公告)日：2011-08-09
申请号：US12805651
申请日：2010-08-11
Applicant: Keun Soo Yim , Jeong-joon Yoo , Young-sam Shin , Seung-won Lee , Han-cheol Kim , Jae-don Lee , Min-kyu Jeong
Inventor： Keun Soo Yim , Jeong-joon Yoo , Young-sam Shin , Seung-won Lee , Han-cheol Kim , Jae-don Lee , Min-kyu Jeong
CPC classification number: G06F8/4441
Abstract: Provided is a method of managing memory in a multiprocessor system on chip (MPSoC). According to an aspect of the present invention, locality of memory can be reflected and restricted memory resources can be efficiently used by determining a storage location of a variable or a function which corresponds to a symbol with reference to a symbol table based on memory access frequency of the variable or the function, comparing the determined storage location and a previous storage location, and copying the variable or the function stored in the previous storage location to the determined storage location if the determined storage location is different from the previous storage location.
Abstract translation: 提供了一种在多处理器片上系统（MPSoC）中管理存储器的方法。 根据本发明的一个方面，通过基于存储器访问频率，参照符号表确定对应于符号的变量或函数的存储位置，可以反映存储器的局部性并且可以有效地使用受限的存储器资源 如果所确定的存储位置与先前存储位置不同，则将所确定的存储位置与先前存储位置进行比较，以及将存储在先前存储位置中的变量或功能复制到所确定的存储位置。
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公开(公告)号：US20110016285A1
公开(公告)日：2011-01-20
申请号：US12591946
申请日：2009-12-04
Applicant: Jae Don Lee , Shi Hwa Lee , Seung Won Lee , Chae Seok Im , Min Kyu Jeong
Inventor： Jae Don Lee , Shi Hwa Lee , Seung Won Lee , Chae Seok Im , Min Kyu Jeong
CPC classification number: G06F12/023 , G06F12/0292
Abstract: Disclosed is a scratch pad memory management device and a method thereof. The scratch pad memory management device divides a scratch pad memory into a plurality of unit blocks, maintains a memory allocation table corresponding to indices of the plurality of unit blocks in a main memory, and manages the scratch pad memory.
Abstract translation: 公开了一种便笺本式存储器管理装置及其方法。 临时存储器管理装置将暂存器存储器划分为多个单位块，维持与主存储器中的多个单位块的索引相对应的存储器分配表，并管理暂存存储器。
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