公开(公告)号：US11301295B1

公开(公告)日：2022-04-12

申请号：US16421434

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Rishi Surendran

IPC: G06F9/46 ,  G06F9/50 ,  G06F16/901 ,  G06F13/28

Abstract: Implementing an application using a plurality of data processing engines (DPEs) can include, in a first pass, mapping, using computer hardware, a data flow graph onto an array of DPEs by minimizing direct memory access (DMA) circuit usage and memory conflicts in the array of DPEs and, in response to determining that a mapping solution generated by the first pass requires an additional DMA circuit not specified by the data flow graph, inserting, using the computer hardware, additional buffers into the data flow graph. In a second pass, the additional buffers can be mapped, using the computer hardware, onto the array of DPEs by minimizing the memory conflicts in the array of DPEs.

公开(公告)号：US20220102293A1

公开(公告)日：2022-03-31

申请号：US17037363

申请日：2020-09-29

Applicant: XILINX, INC.

Inventor： Chi Fung POON ,  Asma LARABA ,  Parag UPADHYAYA

IPC: H01L23/66 ,  H01L25/16 ,  H01L23/538

Abstract: Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.

公开(公告)号：US20220100840A1

公开(公告)日：2022-03-31

申请号：US17034868

申请日：2020-09-28

Applicant: Xilinx, Inc.

Inventor： Dmitriy Shtalenkov ,  Krishnakumar Sugumaran ,  Maurice Penners

IPC: G06F21/35 ,  H04L29/08 ,  G06F9/50

Abstract: An accelerator card can include a read-only memory configured to store a security identifier in a designated field therein and a satellite controller configured to read the security identifier in response to a reset event. The satellite controller is configured to select, based on the security identifier, a security mode from a plurality of security modes and implement the selected security mode in the accelerator card.

公开(公告)号：US11288222B1

公开(公告)日：2022-03-29

申请号：US17035368

申请日：2020-09-28

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Tim Tuan ,  Sridhar Subramanian

IPC: G06F13/40 ,  G06F13/16

Abstract: A multi-die integrated circuit (IC) can include an interposer and a first die coupled to the interposer. The first die can include a data processing engine (DPE) array, wherein the DPE array includes a plurality of DPEs and a DPE interface coupled to the plurality of DPEs. The DPE interface has a logical interface and a physical interface. The multi-die IC also can include a second die coupled to the interposer. The second die can include a die interface. The DPE interface and the die interface are configured to communicate through the interposer.

公开(公告)号：US11270977B2

公开(公告)日：2022-03-08

申请号：US16679063

申请日：2019-11-08

Applicant: XILINX, INC.

Inventor： Praful Jain ,  Steven P. Young ,  Martin L. Voogel ,  Brian C. Gaide

IPC: H01L25/065 ,  H01L25/00

Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.

公开(公告)号：US11256648B1

公开(公告)日：2022-02-22

申请号：US17037396

申请日：2020-09-29

Applicant: XILINX, INC.

Inventor： Chuan Cheng Pan ,  Hanh Hoang ,  Chandrasekhar S. Thyamagondlu

IPC: G06F13/40 ,  G06F13/24 ,  G06F13/42

Abstract: A method for managing a pool of physical functions in a PCIe integrated endpoint includes receiving a configuration instruction indicating a topology for a PCIe connected integrated endpoint (IE), and implementing the topology on the IE. The method further includes receiving a hot plug instruction, and, based at least in part, on the hot plug instruction, adding or removing a virtual endpoint (vEP) to or from a virtual downstream port (vDSP) on the IE.

公开(公告)号：US11245554B1

公开(公告)日：2022-02-08

申请号：US16903377

申请日：2020-06-17

Applicant: XILINX, INC.

Inventor： Hongtao Zhang ,  Winson Lin ,  Arianne Roldan ,  Yohan Frans ,  Geoff Zhang

IPC: H04L25/03 ,  H03L7/089 ,  H04L27/01

Abstract: An example method for clock and data recovery (CDR) includes generating, in a set of slicers of a receiver, in addition to a data signal and a first error signal, at least one additional error signal. The method further includes receiving, at a frequency detector (FD) of a CDR unit of the receiver, the data signal, the first error signal, and the at least one additional error signal, and processing them to generate a FD output. The method still further includes multiplying the FD output by a user-defined FD gain, and adding the FD output, as multiplied by the FD gain, in a frequency path of the CDR unit.

公开(公告)号：US20220035607A1

公开(公告)日：2022-02-03

申请号：US17500509

申请日：2021-10-13

Applicant: Xilinx, Inc.

Inventor： Akella Sastry ,  Vinod K. Kathail ,  L. James Hwang ,  Shail Aditya Gupta ,  Vidhumouli Hunsigida ,  Siddharth Rele

IPC: G06F8/41 ,  H03K19/17724

Abstract: Implementing an application within an integrated circuit (IC) having a data processing engine (DPE) array coupled to a Network-on-Chip (NoC) can include determining, using computer hardware, data transfer requirements for a software portion of the application intended to execute on the DPE array by simulating data traffic to the NoC as generated by the software portion, generating, using the computer hardware, a NoC routing solution for data paths of the application implemented by the NoC based, at least in part, on the data transfer requirements for the software portion. The software portion can be compiled for execution by different ones of a plurality of DPEs of the DPE array based, at least in part, on the NoC routing solution. Configuration data can be generated using the computer hardware. The configuration data, when loaded into the IC, configures the NoC to implement the NoC routing solution.

公开(公告)号：US11218230B2

公开(公告)日：2022-01-04

申请号：US17252686

申请日：2019-06-12

Applicant: XILINX, INC.

Inventor： Michael Grieger ,  Alexandros Pollakis ,  Volker Aue ,  Jan Dohl ,  Ulrich Walther

IPC: H04B17/18 ,  H04B17/12

Abstract: A calibration system for calibrating a number of transceivers, each comprising an in-phase signal path and a quadrature signal path in receive direction and/or in transmit direction is disclosed herein. The calibration system includes a calibration signal generator that is configured to generate a predefined calibration signal for every one of the transceivers, a calibration transceiver that is coupled to the calibration signal generator and to the transceivers and that is configured to supply the generated predefined calibration signals each to the respective transceiver during operation of the transceivers, and/or that is configured to receive the predefined calibration signals after they travel through each one of the transceivers during operation of the transceivers, and a calibration unit that is configured to calibrate the in-phase signal paths and the quadrature signal paths of the transceivers during operation of the transceivers based on the calibration signals as they are received by the transceivers or based on the calibration signals as they are received by the calibration transceiver. Further, an antenna system and a calibration method are also described.

公开(公告)号：US11210148B2

公开(公告)日：2021-12-28

申请号：US16600314

申请日：2019-10-11

Applicant: Xilinx, Inc.

Inventor： Steven Leslie Pope ,  Derek Edward Roberts ,  David James Riddoch ,  Greg Law ,  Steve Grantham ,  Matthew Slattery

IPC: G06F9/54 ,  G06F13/00 ,  H04L12/861 ,  H04L29/06 ,  H04L29/08 ,  G06F15/16 ,  H04L12/879 ,  G06F9/30 ,  G06F13/14

Abstract: A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.