公开(公告)号：US11256648B1

公开(公告)日：2022-02-22

申请号：US17037396

申请日：2020-09-29

Applicant: XILINX, INC.

Inventor： Chuan Cheng Pan ,  Hanh Hoang ,  Chandrasekhar S. Thyamagondlu

IPC: G06F13/40 ,  G06F13/24 ,  G06F13/42

Abstract: A method for managing a pool of physical functions in a PCIe integrated endpoint includes receiving a configuration instruction indicating a topology for a PCIe connected integrated endpoint (IE), and implementing the topology on the IE. The method further includes receiving a hot plug instruction, and, based at least in part, on the hot plug instruction, adding or removing a virtual endpoint (vEP) to or from a virtual downstream port (vDSP) on the IE.

公开(公告)号：US20190243781A1

公开(公告)日：2019-08-08

申请号：US15892266

申请日：2018-02-08

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S Thyamagondlu ,  Darren Jue ,  Tao Yu ,  John West ,  Hanh Hoang ,  Ravi Sunkavalli

IPC: G06F12/1081

CPC classification number: G06F12/1081 ,  G06F2212/621 ,  G06F2213/28

Abstract: Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.

公开(公告)号：US10983920B2

公开(公告)日：2021-04-20

申请号：US15892266

申请日：2018-02-08

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S Thyamagondlu ,  Darren Jue ,  Tao Yu ,  John West ,  Hanh Hoang ,  Ravi Sunkavalli

IPC: G06F12/1081

Abstract: Examples herein describe techniques for providing a customizable direct memory access (DMA) interface which can permit user logic to change or control how DMA read and writes are performed. In one example, a DMA engine may be hardened (e.g., include circuitry formed from a semiconductor material) which prevents the DMA engine from being reconfigured like programmable logic. Instead of changing the DMA engine, the user logic can change or customize the DMA interface between the user logic and the DMA engine. In this way, the manner in which the DMA engine performs DMA write and reads can be changed by the user logic. In one example, the DMA engine includes a bypass mode of operation where descriptors associated with DMA queues are passed through the DMA engine and to the user logic.

公开(公告)号：US10659437B1

公开(公告)日：2020-05-19

申请号：US16144705

申请日：2018-09-27

Applicant: Xilinx, Inc.

Inventor： Ravi Sunkavalli ,  Anujan Varma ,  Chuan Cheng Pan ,  Patrick C. McCarthy ,  Hanh Hoang

IPC: H04L29/06

Abstract: A circuit arrangement includes an encryption circuit and a decryption circuit. A cryptographic shell circuit has a transmit channel and a receive channel in parallel with the transmit channel. The transmit channel includes an encryption interface circuit coupled to the encryption circuit. The encryption interface circuit determines first cryptographic parameters based on data in a plaintext input packet and inputs the first cryptographic parameters and plaintext input packet to the encryption circuit. The receive channel includes a decryption interface circuit coupled to the decryption circuit. The decryption interface circuit determines second cryptographic parameters based on data in a ciphertext input packet and inputs the second cryptographic parameters and ciphertext input packet to the decryption circuit. The encryption circuit encrypts the plaintext input packet based on the first cryptographic parameters, and the decryption circuit decrypts the ciphertext input packet based on the second cryptographic parameters.

公开(公告)号：US10042659B1

公开(公告)日：2018-08-07

申请号：US14067721

申请日：2013-10-30

Applicant: Xilinx, Inc.

Inventor： Ashish Gupta ,  Hanh Hoang ,  Siva Prasad Gadey ,  Kiran S. Puranik

IPC: G06F9/455

Abstract: A method for providing access by a virtual context to a physical instance includes receiving a request to access a physical instance of a plurality of physical instances of a hardware resource of a device. The request is associated with a virtual machine of a plurality of virtual machines. The method next determines that one of the physical instances is available, and assigns a virtual context associated with the virtual machine to access the one of the physical instances when the one of the physical instances is available. The assigning comprises retrieving the virtual context from a memory of the device and loading the virtual context into the one of the physical instances. The method then stores the virtual context in the memory after the one of the physical instances is accessed by the virtual context.