公开(公告)号：US10191759B2

公开(公告)日：2019-01-29

申请号：US15025735

申请日：2013-11-27

Applicant: INTEL CORPORATION

Inventor： David J. Cowperthwaite ,  Murali Ramadoss ,  Ankur N. Shah ,  Balaji Vembu ,  Altug Koker ,  Aditya Navale

IPC: G06F9/455 ,  G06F9/50 ,  G06T1/20

Abstract: In an embodiment, a system includes a graphics processing unit (GPU) that includes one or more GPU engines, and a microcontroller. The microcontroller is to assign a respective schedule slot for each of a plurality of virtual machines (VMs). When a particular VM is scheduled to access a first GPU engine, the particular VM has exclusive access to the first GPU engine. Other embodiments are described and claimed.

公开(公告)号：US20180315399A1

公开(公告)日：2018-11-01

申请号：US15819152

申请日：2017-11-21

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G09G5/36 ,  G06T1/20 ,  G09G5/393 ,  G06N99/00 ,  G06T15/00

CPC classification number: G06F9/3001 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3851 ,  G06F2207/3824 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N20/00 ,  G06T15/005 ,  G09G5/393

Abstract: One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute a 32-bit intermediate product of 16-bit operands and to compute a 32-bit sum based on the 32-bit intermediate product.

公开(公告)号：US20180315398A1

公开(公告)日：2018-11-01

申请号：US15787129

申请日：2017-10-18

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G09G5/36 ,  G06T1/20 ,  G09G5/393

CPC classification number: G06F9/3001 ,  G06F7/483 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3851 ,  G06F2207/3824 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  G06N20/00 ,  G06T15/005 ,  G09G5/393

Abstract: One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.

公开(公告)号：US20180308202A1

公开(公告)日：2018-10-25

申请号：US15495054

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  John C. Weast ,  Mike B. Macpherson ,  Linda L. Hurd ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Liwei Ma ,  Elmoustapha Ould-Ahmed-Vall ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan ,  DUKHWAN Kim

IPC: G06T1/20 ,  G06N3/08

CPC classification number: G06T1/20 ,  G06N3/08

Abstract: A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting, at training time, information relating to one or more tasks to be performed according to a training dataset relating to a processor including a graphics processor. The method may further include analyzing the information to determine one or more portions of hardware relating to the processor capable of supporting the one or more tasks, and configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks.

公开(公告)号：US20180308198A1

公开(公告)日：2018-10-25

申请号：US15493522

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Balaji Vembu ,  Altug Koker ,  Bryan R. White ,  David J. Cowperthwaite ,  Joydeep Ray ,  Murali Ramadoss

IPC: G06T1/20 ,  G06F9/50 ,  G06F9/455

Abstract: An apparatus to facilitate partitioning of a graphics device is disclosed. The apparatus includes a plurality of engines and logic to partition the plurality of engines to facilitate independent access to each engine within the plurality of engines.

公开(公告)号：US20180308197A1

公开(公告)日：2018-10-25

申请号：US15493420

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Balaji Vembu ,  Murali Ramadoss ,  Guei-Yuan Lueh ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu ,  Joydeep Ray ,  Altug Koker ,  James A. Valerio ,  Eric J. Hoekstra ,  Arthur D. Hunter, JR.

IPC: G06T1/20 ,  G06F9/22 ,  G06F9/44 ,  G06T15/04

CPC classification number: G06T1/20 ,  G06F9/223 ,  G06F9/4496 ,  G06T15/04

Abstract: An apparatus to facilitate data intelligent dispatching is disclosed. The apparatus includes one or more processing units including a plurality of execution units (EUs) to execute a plurality of processing threads and collection logic to collect statistics data for threads executed at the processing unit during execution of an application, and dispatch logic to dispatch the threads to be executed at a subset of the plurality of EUs during a subsequent execution of the application based on the statistics data.

公开(公告)号：US20180308196A1

公开(公告)日：2018-10-25

申请号：US15493352

申请日：2017-04-21

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Abhishek R. Appu ,  Subramaniam M. Maiyuran ,  Eric J. Hoekstra ,  Prasoonkumar Surti ,  Balaji Vembu ,  Altug Koker

IPC: G06T1/20 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F9/4831 ,  G06F9/4881 ,  G06F9/505 ,  G06T2210/52

Abstract: A mechanism is described for facilitating thread execution arbitration for thread scheduling relating to graphics processors at computing devices. A method of embodiments, as described herein, includes assigning priority levels to threads based on stall signals communicated from the one or more shared function units to one or more execution units of a processor including a graphics processor, and selecting a first thread to be scheduled and a second thread to be ignored based on the stall signals.

公开(公告)号：US20180307984A1

公开(公告)日：2018-10-25

申请号：US15494971

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Joydeep Ray ,  Balaji Vembu ,  Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Anbang Yao ,  Kevin Nealis ,  Xiaoming Chen ,  John C. Weast ,  Justin E. Gottschlich ,  Prasoonkumar Surti ,  Chandrasekaran Sakthivel ,  Farshad Akhbari ,  Nadathur Rajagopalan Satish ,  Liwei Ma ,  Jeremy Bottleson ,  Eriko Nurvitadhi ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06N3/08 ,  G06N99/00

CPC classification number: G06N3/08 ,  G06F9/28 ,  G06F9/505 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/0481 ,  G06N3/063 ,  G06N99/005

Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180307980A1

公开(公告)日：2018-10-25

申请号：US15494723

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Rajkishore Barik ,  Elmoustapha Ould-Ahmed-Vall ,  Xiaoming Chen ,  Dhawal Srivastava ,  Anbang Yao ,  Kevin Nealis ,  Eriko Nurvitadhi ,  Sara S. Baghsorkhi ,  Balaji Vembu ,  Tatiana Shpeisman ,  Ping T. Tang

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

CPC classification number: G06N3/063 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/084 ,  G06T1/20

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to perform one or more machine learning operations, wherein the decode unit, based on parameters of the one or more machine learning operations, is to request a scheduler to schedule the one or more machine learning operations to one of an array of programmable compute units and a fixed function compute unit.

公开(公告)号：US20180300930A1

公开(公告)日：2018-10-18

申请号：US15488824

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Jonathan Kennedy ,  Gabor Liktor ,  Jeffery S. Boles ,  Slawomir Grajewski ,  Balaji Vembu ,  Travis T. Schluessler ,  Abhishek R. Appu ,  Ankur N. Shah ,  Joydeep Ray ,  Altug Koker ,  Jacek Kwiatkowski

IPC: G06T15/00 ,  A63F13/53

CPC classification number: G06T15/005 ,  A63F13/53 ,  A63F2300/303 ,  A63F2300/66

Abstract: Systems, apparatuses, and methods may provide for technology to process graphics data in a virtual gaming environment. The technology may identify, from graphics data in a graphics application, redundant graphics calculations relating to common frame characteristics of one or more graphical scenes to be shared between client game devices of a plurality of users and calculate, in response to the identified redundant graphics calculations, frame characteristics relating to the one or more graphical scenes. Additionally, the technology may send, over a computer network, the calculation of the frame characteristics to the client game devices.