公开(公告)号：US12141891B2

公开(公告)日：2024-11-12

申请号：US18466991

申请日：2023-09-14

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Nicolas C. Galoppo Von Borries

IPC: G06F12/02 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  G06F17/16 ,  G06F18/2136 ,  G06N3/04 ,  G06N3/08 ,  G06N20/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  H03M7/30

Abstract: Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.

公开(公告)号：US12112397B2

公开(公告)日：2024-10-08

申请号：US18334733

申请日：2023-06-14

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Altug Koker ,  Narayan Srinivasa ,  Dukhwan Kim ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Feng Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Kevin Nealis ,  Xiaoming Chen ,  Anbang Yao

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

CPC classification number: G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

Abstract: One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

公开(公告)号：US11727527B2

公开(公告)日：2023-08-15

申请号：US17541413

申请日：2021-12-03

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha ,  Nadathur Rajagopalan Satish ,  Jeremy Bottleson ,  Farshad Akhbari ,  Altug Koker ,  Narayan Srinivasa ,  Dukhwan Kim ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Feng Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Kevin Nealis ,  Xiaoming Chen ,  Anbang Yao

IPC: G06T1/20 ,  G06N3/063 ,  G06F9/38 ,  G06F9/30 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06T1/20 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3895 ,  G06N3/04 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08 ,  G06N3/084

Abstract: One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex compute operation.

公开(公告)号：US11693658B2

公开(公告)日：2023-07-04

申请号：US17443376

申请日：2021-07-26

Applicant: Intel Corporation

Inventor： Kevin Nealis ,  Anbang Yao ,  Xiaoming Chen ,  Elmoustapha Ould-Ahmed-Vall ,  Sara S. Baghsorkhi ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Kamal Sinha

IPC: G06F9/30 ,  G06F9/38 ,  G06N3/063 ,  G06N3/084 ,  G06T1/20 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06F9/3001 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3893 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06T1/20 ,  G06F2207/4824

Abstract: One embodiment provides for a compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction that specifies multiple operands including a multi-bit input value and a ternary weight associated with a neural network and an arithmetic logic unit including a multiplier, an adder, and an accumulator register. To execute the decoded instruction, the multiplier is to perform a multiplication operation on the multi-bit input based on the ternary weight to generate an intermediate product and the adder is to add the intermediate product to a value stored in the accumulator register and update the value stored in the accumulator register.

公开(公告)号：US11593910B2

公开(公告)日：2023-02-28

申请号：US17741934

申请日：2022-05-11

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06N3/063 ,  G06F9/455 ,  G06F9/50 ,  G06N3/04 ,  G06N3/084 ,  G06F8/41

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

公开(公告)号：US11562461B2

公开(公告)日：2023-01-24

申请号：US17529862

申请日：2021-11-18

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06T15/80 ,  G06F3/14 ,  G06T1/60 ,  G09G5/36 ,  G06F3/06 ,  G06N3/08 ,  G06N3/04 ,  G06N3/063 ,  G09G5/00

Abstract: An apparatus to facilitate compute optimization is disclosed. The apparatus includes one or more processing units to provide a first set of shader operations associated with a shader stage of a graphics pipeline, a scheduler to schedule shader threads for processing, and a field-programmable gate array (FPGA) dynamically configured to provide a second set of shader operations associated with the shader stage of the graphics pipeline.

公开(公告)号：US20230017304A1

公开(公告)日：2023-01-19

申请号：US17874876

申请日：2022-07-27

Applicant: Intel Corporation

Inventor： Rajkishore Barik ,  Brian T. Lewis ,  Murali Sundaresan ,  Jeffrey Jackson ,  Feng Chen ,  Xiaoming Chen ,  Mike Macpherson

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08 ,  G06N5/00 ,  G06F9/46

Abstract: A mechanism is described for facilitating smart distribution of resources for deep learning autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and introducing a library to a neural network application to determine optimal point at which to apply frequency scaling without degrading performance of the neural network application at a computing device.

公开(公告)号：US11488005B2

公开(公告)日：2022-11-01

申请号：US16518828

申请日：2019-07-22

Applicant: Intel Corporation

Inventor： Brian T. Lewis ,  Feng Chen ,  Jeffrey R. Jackson ,  Justin E. Gottschlich ,  Rajkishore Barik ,  Xiaoming Chen ,  Prasoonkumar Surti ,  Mike B. Macpherson ,  Murali Sundaresan

IPC: G01C22/00 ,  G06N3/063 ,  B60W30/095 ,  G06N3/00 ,  G06N3/04 ,  G01C21/34

Abstract: A mechanism is described for facilitating smart collection of data and smart management of autonomous machines. A method of embodiments, as described herein, includes detecting one or more sets of data from one or more sources over one or more networks, and combining a first computation directed to be performed locally at a local computing device with a second computation directed to be performed remotely at a remote computing device in communication with the local computing device over the one or more networks, where the first computation consumes low power, wherein the second computation consumes high power.

公开(公告)号：US20210217130A1

公开(公告)日：2021-07-15

申请号：US17193658

申请日：2021-03-05

Applicant: Intel Corporation

Inventor： Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Nicolas C. Galoppo Von Borries

IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0888 ,  H03M7/30 ,  G06K9/62 ,  G06N20/00 ,  G06F9/48 ,  G06F17/16 ,  G06N3/04 ,  G06N3/08 ,  G06T1/60 ,  G06T15/00

Abstract: Techniques to improve performance of matrix multiply operations are described in which a compute kernel can specify one or more element-wise operations to perform on output of the compute kernel before the output is transferred to higher levels of a processor memory hierarchy.

公开(公告)号：US11017291B2

公开(公告)日：2021-05-25

申请号：US15581031

申请日：2017-04-28

Applicant: Intel Corporation

Inventor： Brian T. Lewis ,  Rajkishore Barik ,  Murali Sundaresan ,  Leonard Truong ,  Feng Chen ,  Xiaoming Chen ,  Mike B. Macpherson

IPC: G06N3/00 ,  G06N3/063 ,  G06N3/04 ,  G06F7/483 ,  G06N3/08

Abstract: A mechanism is described for facilitating efficient training of neural networks at computing devices. A method of embodiments, as described herein, includes detecting one or more inputs for training of a neural network, and introducing randomness in floating point (FP) numbers to prevent overtraining of the neural network, where introducing randomness includes replacing less-significant low-order bits of operand and result values with new low-order bits during the training of the neural network.