公开(公告)号：US20220076748A1

公开(公告)日：2022-03-10

申请号：US17530676

申请日：2021-11-19

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C16/04 ,  H01L27/1156 ,  G11C16/26 ,  G11C16/10

Abstract: The present disclosure includes apparatuses, methods, and systems for preventing parasitic current during program operations in memory. An embodiment includes a sense line, an access line, and a memory cell. The memory cell includes a first transistor having a floating gate and a control gate, wherein the control gate of the first transistor is coupled to the access line, and a second transistor having a control gate, wherein the control gate of the second transistor is coupled to the access line, a first node of the second transistor is coupled to the sense line, and a second node of the second transistor is coupled to the floating gate of the first transistor. The memory cell also includes a diode, or other rectifying element, coupled to the sense line and a node of the first transistor.

公开(公告)号：US20220076724A1

公开(公告)日：2022-03-10

申请号：US17470573

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Xinwei Guo ,  Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for digit line management for a memory array are described. A memory array may include a plate that is common to a plurality of memory cells. Each memory cell associated with the common plate may be coupled with a respective digit line. One or more memory cells common to the plate may be accessed by concurrently selecting the plate and each digit line associated with the plate. Concurrent selection of all digit lines associated with the plate may be supported by shield lines between the selected digit lines. Additionally or alternatively, selection of all digit lines associated with the plate may be supported by improved sensing schemes and related amplifier configurations.

公开(公告)号：US11244733B2

公开(公告)日：2022-02-08

申请号：US16685309

申请日：2019-11-15

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Mark Fischer ,  Adam D. Johnson

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C11/22

Abstract: Methods, systems, and devices for techniques to mitigate disturbances of unselected memory cells in a memory array during an access operation are described. A shunt line may be formed between a plate of a selected memory cell and a digit line of the selected memory cell to couple the plate to the digit line during the access operation. A switching component may be positioned on the shunt line. The switching component may selectively couple the plate to the digit line based on instructions received from a memory controller. By coupling the plate to the digit line during the access operation, voltages resulting on the plate by changes in the voltage level of the digit line may be reduced in magnitude or may be altered in type.

公开(公告)号：US11120859B2

公开(公告)日：2021-09-14

申请号：US16107925

申请日：2018-08-21

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection component that is in electronic communication with a sense amplifier and a ferroelectric capacitor of a ferroelectric memory cell. A voltage applied to the ferroelectric capacitor may be sized to increase the signal sensed during a read operation. The ferroelectric capacitor may be isolated from the sense amplifier during the read operation. This isolation may avoid stressing the ferroelectric capacitor which may otherwise occur due to the applied read voltage and voltage introduce by the sense amplifier during the read operation.

公开(公告)号：US20210264960A1

公开(公告)日：2021-08-26

申请号：US17196650

申请日：2021-03-09

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Daniele Vimercati ,  Duane R. Mills

IPC: G11C11/22 ,  G06F11/10

Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.

公开(公告)号：US20210193211A1

公开(公告)日：2021-06-24

申请号：US17187310

申请日：2021-02-26

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22 ,  G11C13/00

Abstract: The present disclosure includes apparatuses, methods, and systems for current separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell having a ferroelectric material, and determining a data state of the memory cell by separating a first current output by the memory cell while the sensing voltage is being applied to the memory cell and a second current output by the memory cell while the sensing voltage is being applied to the memory cell, wherein the first current output by the memory cell corresponds to a first polarization state of the ferroelectric material of the memory cell and the second current output by the memory cell corresponds a second polarization state of the ferroelectric material of the memory cell.

公开(公告)号：US10958271B1

公开(公告)日：2021-03-23

申请号：US16922894

申请日：2020-07-07

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: H03K19/003 ,  G11C7/10 ,  H03K19/0185

Abstract: An electronic device may include one or more output buffers each including a pair of final p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS) transistors, a first pre-buffer to drive the PMOS transistor, and a second pre-buffer to drive the NMOS transistor. Each output buffer receives power from a pre-buffer supply filtering circuit, which may include a supply capacitor for stabilizing supply voltage, a low-pass first pre-buffer supply filter to filter the voltage supplied to the first pre-buffer, and a low-pass second pre-buffer supply filter the voltage supplied to the second pre-buffer.

公开(公告)号：US10943633B2

公开(公告)日：2021-03-09

申请号：US16583033

申请日：2019-09-25

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Xinwei Guo

IPC: G11C11/22 ,  G11C29/00 ,  G11C11/56

Abstract: Methods, systems, and apparatuses for redundancy in a memory array are described. A memory array may include some memory cells that are redundant to other memory cells of the array. Such redundant memory cells may be used if a another memory cell is discovered to be defective in some way; for example, after the array is fabricated and before deployment, defects in portions of the array that affect certain memory cells may be identified. Memory cells may be designated as redundant cells for numerous other memory cells of the array so that a total number of redundant cells in the array is relatively small fraction of the total number of cells of the array. A configuration of switching components may allow redundant cells to be operated in a manner that supports redundancy for numerous other cells and may limit or disturbances to neighboring cells when accessing redundancy cells.

公开(公告)号：US20200279590A1

公开(公告)日：2020-09-03

申请号：US16877133

申请日：2020-05-18

Applicant: Micron Technology, Inc

Inventor： Mahdi Jamali ,  William A. Melton ,  Daniele Vimercati ,  Xinwei Guo ,  Yasuko Hattori

IPC: G11C7/06 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/22

Abstract: Methods, systems, and devices for self-referencing sensing schemes with coupling capacitance are described. A sense component of a memory device may include a capacitive coupling between two nodes of the sense component. The capacitive coupling may, in some examples, be provided by a capacitive element of the sense component or an intrinsic capacitance between features of the sense component. An example of a method employing such a sense component for detecting a logic state stored by a memory cell may include generating a first sense signal at one of the nodes while the node is coupled with the memory cell, and generating a second sense signal at the other of the nodes while the other node is coupled with the memory cell. The sense signals may be based at least in part on the capacitive coupling between the two nodes.

公开(公告)号：US20200265885A1

公开(公告)日：2020-08-20

申请号：US16866204

申请日：2020-05-04

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further include a first capacitor coupled to the first transistor and a second capacitor coupled to the second transistor and a first switching component coupled between a voltage source and the first capacitor and the second capacitor. For example, the first switching component may be activated, a reference voltage may be applied to the sense component, and the first switching component may then be deactivated. In some examples, a voltage offset may be measured across both the first and the second capacitor.