公开(公告)号：US20240194251A1

公开(公告)日：2024-06-13

申请号：US18499934

申请日：2023-11-01

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Christopher K. Morzano ,  Daniele Vimercati

IPC: G11C11/4097

CPC classification number: G11C11/4097

Abstract: Devices and methods for operating a memory device including multiple memory cells configured to store data and multiple global digit lines configured to carry the data in memory accesses of the memory cells. The memory device also includes multiple local digit lines configured to carry the data between the global digit lines and the memory cells. The memory device further includes multiple digit line selection circuits configured to selectively couple selected local digit lines of the local digit lines to the global digit lines. The memory device also includes a controller configured to select a pattern of selected digit line selection circuits to at least partially cancel capacitive coupling between the selected local digit lines.

公开(公告)号：US20240081036A1

公开(公告)日：2024-03-07

申请号：US18369606

申请日：2023-09-18

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal

IPC: H10B10/00 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B10/125 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66742 ,  H01L29/78642

Abstract: Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.

公开(公告)号：US20230397398A1

公开(公告)日：2023-12-07

申请号：US17805201

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Richard E. Fackenthal

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10897 ,  H01L27/1085 ,  H01L27/10873

Abstract: A microelectronic device comprises vertical stacks of memory cells, each vertical stack of memory cells comprising a vertical stack of access devices, a vertical stack of capacitors horizontally neighboring the vertical stack of access devices, and a conductive pillar structure vertically extending through the vertical stack of access devices. The microelectronic device further comprises multiplexers and additional transistors vertically overlying the vertical stacks of memory cells, and global digit lines vertically overlying the multiplexer and the additional transistor. Related electronic systems and methods are also described.

公开(公告)号：US11800696B2

公开(公告)日：2023-10-24

申请号：US17824434

申请日：2022-05-25

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal

IPC: G11C11/40 ,  H10B10/00 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

CPC classification number: H10B10/125 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H10B10/18

Abstract: Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.

公开(公告)号：US20230299163A1

公开(公告)日：2023-09-21

申请号：US17655479

申请日：2022-03-18

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Karthik Sarpatwari ,  Richard E. Fackenthal

IPC: H01L29/423 ,  H01L27/02 ,  H01L27/11 ,  G11C5/02 ,  H01L27/092

CPC classification number: H01L29/42372 ,  G11C5/025 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/1104

Abstract: An inverter includes a transistor, an additional transistor overlying the transistor, and a hybrid gate electrode interposed between and shared by the transistor and the additional transistor. The hybrid gate electrode includes a region overlying a channel structure of the transistor, an additional region overlying the region and underlying an additional channel structure of the additional transistor, and further region interposed between the region and the additional region. The region has a first material composition. The additional region has a second material composition different than the first material composition of the region. Memory devices and electronic systems are also described.

公开(公告)号：US20220359540A1

公开(公告)日：2022-11-10

申请号：US17824434

申请日：2022-05-25

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.

公开(公告)号：US11301320B2

公开(公告)日：2022-04-12

申请号：US16840286

申请日：2020-04-03

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Angelo Visconti

IPC: G06F11/10 ,  G06F13/28 ,  G06F11/30 ,  G06F11/16 ,  G11C11/22 ,  G11C11/4091

Abstract: Methods, systems, and devices for erasure decoding for a memory device are described. In accordance with the described techniques, a memory device may be configured to identify conditions associated with an erasure, a possible erasure, or an otherwise indeterminate logic state (e.g., of a memory cell, of an information position of a codeword). Such an identification may be used to enhance aspects of error handling operations, including those that may be performed at the memory device or a host device (e.g., error handling operations performed at a memory controller external to the memory device). For example, error handling operations may be performed using speculative codewords, where information positions associated with an indeterminate or unassigned logic state are assigned with a respective assumed logic state, which may extend a capability of error detection or error correction compared to handling errors with unknown positions.

公开(公告)号：US11183241B2

公开(公告)日：2021-11-23

申请号：US17111019

申请日：2020-12-03

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

Abstract: Methods, systems, and devices for source line configurations for a memory device are described. In some cases, a memory cell of the memory device may include a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled with the floating gate of the first transistor. The memory cell may be coupled with a word line, a digit line, and a source line. During a write operation, the source line may be clamped to the digit line using one or more memory cells in the memory device. During a read operation, the source line may be grounded using one or more memory cells in the memory device.

公开(公告)号：US10971203B2

公开(公告)日：2021-04-06

申请号：US16504837

申请日：2019-07-08

Applicant: Micron Technology, Inc.

Inventor： Richard E. Fackenthal ,  Daniele Vimercati ,  Duane R. Mills

IPC: G11C29/00 ,  G11C11/22 ,  G06F11/10 ,  G11C29/52

Abstract: Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.

公开(公告)号：US10861579B2

公开(公告)日：2020-12-08

申请号：US16513018

申请日：2019-07-16

Applicant: Micron Technology, Inc.

Inventor： Simon J. Lovett ,  Richard E. Fackenthal

IPC: G11C11/22 ,  G11C29/50 ,  G11C29/00

Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.