公开(公告)号：US11523264B2

公开(公告)日：2022-12-06

申请号：US17002501

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Danilo Caraccio

IPC: H04B5/00 ,  H04W4/80 ,  H04W4/00 ,  G06F12/1027 ,  G06F12/10 ,  H04L45/74 ,  H04L41/0853

Abstract: Systems and methods for vendor-agnostic access to non-volatile memory of a wireless memory tag are provided. A wireless memory host includes a radio and controller. The controller generates vendor-agnostic commands to access a register-based interface that ultimately results in access to the non-volatile memory.

公开(公告)号：US11488681B2

公开(公告)日：2022-11-01

申请号：US17170386

申请日：2021-02-08

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Dallabora ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C13/00 ,  G11C7/22 ,  G06F11/10 ,  G11C29/04

Abstract: An example apparatus includes a memory comprising a plurality of managed units corresponding to respective groups of resistance variable memory cells and a controller coupled to the memory. The controller is configured to cause performance of a cleaning operation on a selected group of the memory cells and generation of error correction code (ECC) parity data. The controller may be further configured to cause performance of a write operation on the selected group of cells to write an inverted state of at least one data value to the selected group of cells and write an inverted state of at least one of the ECC parity data to the selected group of cells.

公开(公告)号：US11456033B2

公开(公告)日：2022-09-27

申请号：US16846481

申请日：2020-04-13

Applicant: Micron Technology, Inc.

Inventor： Daniele Balluchi ,  Paolo Amato ,  Graziano Mirichigni ,  Danilo Caraccio ,  Marco Sforzin ,  Marco Dallabora

IPC: G11C11/00 ,  G11C13/00

Abstract: An apparatus can have a memory comprising an array of resistance variable memory cells and a controller. The controller can be configured to receive to a dedicated command to write all cells in a number of groups of the resistance variable memory cells to a first state without transferring any host data corresponding to the first state to the number of groups. The controller can be configured to, in response to the dedicated command, perform a read operation on each respective group to determine states of the cells in each respective group, determine from the read operation any cells in each respective group programmed to a second state, and write only the cells determined to be in the second state to the first state.

公开(公告)号：US11327892B2

公开(公告)日：2022-05-10

申请号：US16893982

申请日：2020-06-05

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora ,  Roberto Izzi ,  Paolo Amato ,  Daniele Balluchi ,  Luca Porzio

IPC: G06F12/0862 ,  G06F12/10 ,  G06F3/06

Abstract: An example apparatus comprises a hybrid memory system and a controller coupled to the hybrid memory system. The controller may be configured to cause data to be selectively stored in the hybrid memory system responsive to a determination that an exception involving the data has occurred.

公开(公告)号：US11275508B2

公开(公告)日：2022-03-15

申请号：US16361445

申请日：2019-03-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Francesco Falanga ,  Danilo Caraccio

IPC: G06F3/06 ,  G06F12/02

Abstract: Methods for automatically performing a background operation in a memory device might include automatically performing the background operation responsive to automatic performance of the background operation being enabled and receiving a start command.

公开(公告)号：US20220035701A1

公开(公告)日：2022-02-03

申请号：US17375832

申请日：2021-07-14

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Daniele Balluchi

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02

Abstract: Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.

公开(公告)号：US20220027085A1

公开(公告)日：2022-01-27

申请号：US16937213

申请日：2020-07-23

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Roberto Izzi ,  Nicola Colella ,  Danilo Caraccio ,  Alessandro Orlando

IPC: G06F3/06 ,  G06F12/06

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.

公开(公告)号：US20210406411A1

公开(公告)日：2021-12-30

申请号：US16765224

申请日：2019-05-21

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Marco Sforzin ,  Daniele Balluchi ,  Danilo Caraccio ,  Niccolo Izzo

IPC: G06F21/85 ,  G06F21/79 ,  G06F21/60 ,  G06F12/02

Abstract: The present disclosure relates to apparatuses and methods for memory management. The disclosure further relates to an interface protocol for flash memory devices including at least a memory array and a memory controller coupled to the memory array.
A host device is coupled to the memory device through a communication channel and a hardware and/or software full encryption-decryption scheme is adopted in the communication channel for data, addresses and commands exchanged between the host device and the memory array.

公开(公告)号：US11209986B2

公开(公告)日：2021-12-28

申请号：US16541571

申请日：2019-08-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Marco Dallabora

IPC: G06F11/10 ,  G06F12/1009 ,  G11C16/34 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to memory operations on data. An example method can include executing an operation by writing a first managed unit to a second managed unit, and placing the first managed unit in a free state, wherein the first managed unit is located at a particular distance from the second managed unit.

公开(公告)号：US20210208988A1

公开(公告)日：2021-07-08

申请号：US17206881

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Marco Dallabora ,  Emanuele Confalonieri ,  Paolo Amato ,  Daniele Balluchi ,  Danilo Caraccio

IPC: G06F11/20 ,  G06F3/06

Abstract: The present disclosure includes apparatuses and methods related to hybrid memory management. An example apparatus can include a first memory array, a number of second memory arrays, and a controller coupled to the first memory array and the number of second memory arrays configured to execute a write operation, wherein execution of the write operation writes data to the first memory array starting at a location indicated by a write cursor, and place the write cursor at an updated location in the first memory array upon completing execution of the write operation, wherein the updated location is a next available location in the first memory array.