公开(公告)号：US11340836B2

公开(公告)日：2022-05-24

申请号：US16990864

申请日：2020-08-11

Applicant: Micron Technology, Inc.

Inventor： Angelo Della Monica ,  Eric Kwok Fung Yuen ,  Pasquale Cimmino ,  Massimo Iaculo ,  Francesco Falanga

IPC: G06F3/06

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US08904250B2

公开(公告)日：2014-12-02

申请号：US13767389

申请日：2013-02-14

Applicant: Micron Technology, Inc.

Inventor： Francesco Falanga ,  Victor Tsai

IPC: G11C29/00 ,  G11C29/44

CPC classification number: G11C29/38 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0407 ,  G11C2029/0409

Abstract: Testing methods in a pre-programmed memory device after it has been assembled into a final customer platform include issuing a self-test command to the memory device, the memory device reporting results of a self-test of pre-programmed data executed responsive to receiving the self-test command, and issuing a self-repair command responsive to the results indicating repair of the pre-programmed data is needed.

Abstract translation: 预先编程的存储器件中的测试方法已经被组装到最终的客户平台中之后，包括向存储器件发出自检命令，该存储器件报告响应于接收执行的预编程数据的自检的结果 自检命令，并且响应于指示预编程数据的修复的结果发出自修复命令。

公开(公告)号：US20240303087A1

公开(公告)日：2024-09-12

申请号：US18609981

申请日：2024-03-19

Applicant: Micron Technology, Inc.

Inventor： Francesco Basso ,  Giuseppe Ferrari ,  Francesco Falanga ,  Massimo Iaculo

IPC: G06F9/4401 ,  G06F12/0871

CPC classification number: G06F9/4406 ,  G06F12/0871

Abstract: Methods, systems, and devices for data caching for fast system boot-up are described. A memory system may create a linked mapping of addresses, which may also be referred to as a mixed page pointer table. The linked mapping may include logical addresses associated with commands received during a boot-up procedure, and their associated physical addresses. The linked mapping may also include a counter associated with each logical address to track how often the logical address is referenced during successive boot-up procedures. Over successive boot-up procedures, addresses may be added or removed from the linked mapping, and sequential addresses may be compressed. The memory device may use the linked mapping to predict which data may be accessed during the boot-up procedure, and may pre-transfer the data to volatile memory based on the prediction.

公开(公告)号：US20240086070A1

公开(公告)日：2024-03-14

申请号：US17931416

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Francesco Basso ,  Francesco Falanga ,  Alberto Sassara ,  Massimo Iaculo

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0629 ,  G06F3/0673

Abstract: Methods, systems, and devices for read disturb management for memory are described. In some instances, data may be read from a first page of a virtual block of a memory system. If the data includes one or more errors, the memory system may read data from a second page of the virtual block and determine whether one or more errors exist in the data. The memory system may continue reading pages of the virtual block until a page includes no (or relatively few errors). The memory system may then refresh the pages.

公开(公告)号：US20220276808A1

公开(公告)日：2022-09-01

申请号：US17747477

申请日：2022-05-18

Applicant: Micron Technology, Inc.

Inventor： Angelo Della Monica ,  Eric Kwok Fung Yuen ,  Pasquale Cimmino ,  Massimo Iaculo ,  Francesco Falanga

IPC: G06F3/06

Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20170133105A1

公开(公告)日：2017-05-11

申请号：US15412148

申请日：2017-01-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Francesco Falanga ,  Victor Tsai

IPC: G11C29/38 ,  G11C29/44 ,  G11C16/04 ,  G11C29/36

CPC classification number: G11C29/38 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0407 ,  G11C2029/0409

Abstract: Methods of managing systems comprising a processor and a memory device external to the processor, including exposing the memory device to temperature levels associated with soldering, starting up the memory device and testing pre-programmed data using control circuitry of the memory device. When results of the testing indicate repair of the pre-programmed data should be performed, issuing a command from the processor to the memory device indicative of a desire for the memory device to repair the pre-programmed data, and in response to the memory device receiving the command, repairing the pre-programmed data using the control circuitry of the memory device.

公开(公告)号：US09329990B2

公开(公告)日：2016-05-03

申请号：US13739453

申请日：2013-01-11

Applicant: Micron Technology, Inc.

Inventor： Francesco Falanga ,  Danilo Caraccio

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/0246 ,  G06F2212/7211

Abstract: A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations. The host can enable the automatic background operations if the memory device supports this feature. The host can then set a time period in the memory device that is indicative of when the memory device can automatically perform the background operations.

Abstract translation: 耦合到存储设备的主机被配置为读取存储器设备的状态寄存器以确定存储器设备是否支持主机控制的自动后台操作的启用。 存储器设备响应于主机是否支持主机控制启用自动后台操作。 如果内存设备支持此功能，主机可以启用自动后台操作。 然后，主机可以在存储器设备中设置指示存储器设备何时可以自动执行后台操作的时间段。

公开(公告)号：US20140229777A1

公开(公告)日：2014-08-14

申请号：US13767389

申请日：2013-02-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Francesco Falanga ,  Victor Tsai

IPC: G11C29/44

CPC classification number: G11C29/38 ,  G11C16/0483 ,  G11C16/3418 ,  G11C29/36 ,  G11C29/4401 ,  G11C29/52 ,  G11C2029/0407 ,  G11C2029/0409

Abstract: Testing methods in a pre-programmed memory device after it has been assembled into a final customer platform include issuing a self-test command to the memory device, the memory device reporting results of a self-test of pre-programmed data executed responsive to receiving the self-test command, and issuing a self-repair command responsive to the results indicating repair of the pre-programmed data is needed.

Abstract translation: 预先编程的存储器件中的测试方法已经被组装到最终的客户平台中之后，包括向存储器件发出自检命令，该存储器件报告响应于接收执行的预编程数据的自检的结果 自检命令，并且响应于指示预编程数据的修复的结果发出自修复命令。

公开(公告)号：US12039189B2

公开(公告)日：2024-07-16

申请号：US17900361

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Francesco Basso ,  Antonino Pollio ,  Francesco Falanga ,  Massimo Iaculo

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0604 ,  G06F3/0652 ,  G06F3/0679

Abstract: Methods, systems, and devices for idle mode temperature control for memory systems are described. A memory system may implement the use of one or more dummy access commands to reduce the effects of errors introduced by temperature changes while the memory system is in an idle mode. For example, performing one or more access commands, such as one or more read commands, may increase a temperature of a memory device and support a desired operating temperature for the memory device while the memory system is in the idle mode. The memory system may measure the temperature of the memory device during the idle mode. If the memory system determines that the temperature of the memory device has fallen below a threshold temperature, the memory system may issue a quantity of dummy access commands to the memory device, and the corresponding dummy access operations may result in a temperature increase at the memory device.

公开(公告)号：US20230195474A1

公开(公告)日：2023-06-22

申请号：US17645685

申请日：2021-12-22

Applicant: Micron Technology, Inc.

Inventor： Francesco Basso ,  Giuseppe Ferrari ,  Francesco Falanga ,  Massimo Iaculo

IPC: G06F9/4401 ,  G06F12/0871

CPC classification number: G06F9/4406 ,  G06F12/0871

Abstract: Methods, systems, and devices for data caching for fast system boot-up are described. A memory system may create a linked mapping of addresses, which may also be referred to as a mixed page pointer table. The linked mapping may include logical addresses associated with commands received during a boot-up procedure, and their associated physical addresses. The linked mapping may also include a counter associated with each logical address to track how often the logical address is referenced during successive boot-up procedures. Over successive boot-up procedures, addresses may be added or removed from the linked mapping, and sequential addresses may be compressed. The memory device may use the linked mapping to predict which data may be accessed during the boot-up procedure, and may pre-transfer the data to volatile memory based on the prediction.