公开(公告)号：US6100554A

公开(公告)日：2000-08-08

申请号：US879534

申请日：1997-06-20

申请人： Yohei Ishikawa ,  Koichi Sakamoto

发明人： Yohei Ishikawa ,  Koichi Sakamoto

IPC分类号： H01L29/772 ,  H01L21/338 ,  H01L23/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/76 ,  H01L29/812 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L29/8122 ,  H01L23/66 ,  H01L29/41725 ,  H01L29/42316 ,  H01L2924/0002 ,  H01L2924/3011

摘要： An intrinsic device section is provided by laminating a drain area, an intermediate area, and a source area above a GaAs substrate and by forming a channel area at one oblique surface thereof. A drain electrode ohmic connected to the drain area extends toward the output side, a source electrode ohmic connected to the source area extends above the drain electrode with a dielectric layer placed therebetween, and thereby an output micro-wave transmission line is formed. A gate electrode Schottky connected to the channel area extends toward the input side, the source electrode extends above the drain electrode with the dielectric layer placed therebetween, and thereby an input micro-wave transmission line formed.

摘要翻译： 通过在GaAs衬底上层叠漏极区域，中间区域和源极区域并且在其一个倾斜表面上形成沟道区域来提供本征器件部分。 连接到漏极区域的欧姆电极的漏极朝向输出侧延伸，与源极区欧姆连接的源极延伸到漏电极的上方，其间放置介电层，从而形成输出微波传输线。 连接到沟道区的栅极电极肖特基向着输入侧延伸，源极延伸到漏电极的上方，介电层位于它们之间，从而形成输入微波传输线。

公开(公告)号：US5672904A

公开(公告)日：1997-09-30

申请号：US708094

申请日：1996-08-23

申请人： Tomoyasu Miyata ,  Koichi Sakamoto

发明人： Tomoyasu Miyata ,  Koichi Sakamoto

IPC分类号： H01L21/329 ,  H01L29/47 ,  H01L29/861 ,  H01L29/872 ,  H01L23/58

CPC分类号： H01L29/66212 ,  H01L29/872

摘要： A Schottky barrier diode having improved breakdown characteristics has an n.sup.+ semiconductor layer and an n.sup.- semiconductor layer provided on the n.sup.+ semiconductor layer. The n.sup.- semiconductor layer is configured to form a mesa. An insulating layer is formed so as to expose the upper surface of the mesa. An anode electrode is provided on the exposed surface and a side surface of the mesa, while a cathode is electrically connected to the n.sup.+ layer. A plasma treated layer is provided in the n.sup.- semiconductor layer so as to extend inwardly from at least a portion of the side surface of the mesa.

摘要翻译： 具有改进的击穿特性的肖特基势垒二极管具有设置在n +半导体层上的n +半导体层和n-半导体层。 n型半导体层被配置成形成台面。 形成绝缘层以暴露台面的上表面。 阳极电极设置在暴露表面和台面的侧表面上，而阴极电连接到n +层。 在n-半导体层中设置等离子体处理层，以便从台面的侧表面的至少一部分向内延伸。