公开(公告)号：US6144589A

公开(公告)日：2000-11-07

申请号：US186758

申请日：1998-11-05

申请人： Rino Micheloni ,  Giovanni Campardo ,  Donato Ferrario ,  Carla Maria Golla

发明人： Rino Micheloni ,  Giovanni Campardo ,  Donato Ferrario ,  Carla Maria Golla

IPC分类号： G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C7/00

CPC分类号： G11C16/08 ,  G11C8/08 ,  G11C8/10

摘要： A boosting circuit supplied by a first voltage level and a second voltage level, and having an output line capable of taking a third voltage level, the circuit having at least two distinct circuits for generating the third voltage level, the at least two circuits selectively activatable for generating the third voltage level and selectively coupleable to the output line.

摘要翻译： 由第一电压电平和第二电压电平提供的升压电路，并具有能够获得第三电压电平的输出线，所述电路具有用于产生第三电压电平的至少两个不同的电路，所述至少两个电路可选择地激活 用于产生第三电压电平并选择性地耦合到输出线。

公开(公告)号：US6122200A

公开(公告)日：2000-09-19

申请号：US200002

申请日：1998-11-25

申请人： Giovanni Campardo ,  Rino Micheloni

发明人： Giovanni Campardo ,  Rino Micheloni

IPC分类号： G11C16/02 ,  G11C16/08 ,  G11C16/04

CPC分类号： G11C16/08

摘要： A row decoder includes a plurality of pre-decoding circuits which, starting from row addresses, generate pre-decoding signals and a plurality of final decoding circuits which, starting from the pre-decoding signals, drive the individual rows of the array of the memory device. Each pre-decoding circuit has a push-pull output circuit with a pull-up transistor and a pull-down transistor and four parallel paths for the signal, a first path, supplied with low voltage, which drives the pull-up transistor during reading; a second path, supplied with a positive high voltage, which drives the pull-up transistor during programming and erasing; a third path, supplied with a low voltage, which drives the pull-down transistor during reading and programming; and a fourth path, supplied with a negative high voltage, which drives the pull-down transistor during erasing. Two selection stages enable selectively one of the first and second path, and one of the third and fourth path, depending on the operative step.

摘要翻译： 行解码器包括多个预解码电路，其从行地址开始产生预解码信号，并且从预解码信号开始，驱动存储器的阵列的各行，多个最终​​解码电路 设备。 每个预译码电路都具有一个具有上拉晶体管和一个下拉晶体管的推挽输出电路，以及四个用于该信号的并行通路，一个提供低电压的第一路径，其在读取期间驱动上拉晶体管 ; 第二路径被提供有正高电压，其在编程和擦除期间驱动上拉晶体管; 提供低电压的第三路径，其在读取和编程期间驱动下拉晶体管; 以及提供有负高电压的第四路径，其在擦除期间驱动下拉晶体管。 根据操作步骤，两个选择阶段能够选择性地选择第一和第二路径之一以及第三和第四路径中的一个。

公开(公告)号：US5903498A

公开(公告)日：1999-05-11

申请号：US877927

申请日：1997-06-18

申请人： Giovanni Campardo ,  Rino Micheloni ,  Stefano Commodaro

发明人： Giovanni Campardo ,  Rino Micheloni ,  Stefano Commodaro

IPC分类号： G11C16/08 ,  G11C7/00

CPC分类号： G11C16/08

摘要： The memory device has a plurality of local boost circuits, each connected to a sector of the memory array, and each having a control circuit, at least a respective boost capacitor, and a respective drive circuit. Each drive circuit is only enabled in read mode, on receiving an address-transition-detect signal and a sector enabling signal, for reading memory cells forming part of the respective sector. The boost voltage is only supplied to the final inverter of the row decoder. A clamping diode limits the boost voltage to prevent undesired direct biasing of the PMOS transistors of the final inverters connected to the nonaddressed word lines. And the overvoltage is therefore only supplied locally when and where necessary.

摘要翻译： 存储器件具有多个本地升压电路，每个局部升压电路各自连接到存储器阵列的扇区，并且每个具有控制电路，至少相应的升压电容器和相应的驱动电路。 每个驱动电路仅在读取模式下被启用，在接收到地址转换检测信号和扇区使能信号时，用于读取形成相应扇区的一部分的存储器单元。 升压电压仅提供给行解码器的最终反相器。 钳位二极管限制升压电压，以防止连接到非寻址字线的最终逆变器的PMOS晶体管的不期望的直接偏置。 因此，过电压仅在必要时在当地提供。