公开(公告)号：US20100289445A1

公开(公告)日：2010-11-18

申请号：US12779591

申请日：2010-05-13

Applicant: Fulvio Giacomo BAGARELLI ,  Vincenzo Marano ,  Enrico Poli

Inventor： Fulvio Giacomo BAGARELLI ,  Vincenzo Marano ,  Enrico Poli

IPC: H02P8/14 ,  H02P8/38

CPC classification number: H02P8/12 ,  H02P8/22

Abstract: A method of driving a stepper motor in a feed-forward voltage mode may include for a desired speed for the stepper motor setting an amplitude of a sinusoidal phase voltage of the stepper motor to be equal to a sum of an expected back-electromotive force (BEMF) amplitude estimated as a junction of the desired speed, and a product of a desired phase current amplitude and an estimated absolute value of an impedance of the stepper motor.

Abstract translation: 在前馈电压模式下驱动步进电动机的方法可以包括步进电动机的期望速度，使步进电动机的正弦相电压的幅度等于预期的反电动势（ BEMF）幅度估计为期望速度的结，以及期望的相电流幅度与步进电动机的阻抗的估计绝对值的乘积。

公开(公告)号：US20100245148A1

公开(公告)日：2010-09-30

申请号：US12719424

申请日：2010-03-08

Applicant: Santi Carlo ADAMO ,  Vincent Onde ,  Francesco Bombaci ,  Orazio Musumeci

Inventor： Santi Carlo ADAMO ,  Vincent Onde ,  Francesco Bombaci ,  Orazio Musumeci

IPC: H03M1/12

CPC classification number: G06F13/28

Abstract: An analog-digital converter for converting an analog signal into a digital signal includes a first configuration register for configuring a first group of channels and a second configuration register for configuring a second group of channels. The conversion result of the channels of the first group is transferred to a memory via a direct memory access. Each channel of the second group of channels has an associated respective data register and the conversion results of the channels of the second group are stored in the respective data registers.

Abstract translation: 一种用于将模拟信号转换为数字信号的模拟数字转换器包括用于配置第一组信道的第一配置寄存器和用于配置第二组信道的第二配置寄存器。 第一组的通道的转换结果通过直接存储器访问传送到存储器。 第二组信道的每个信道具有关联的相应的数据寄存器，并且第二组的信道的转换结果存储在相应的数据寄存器中。

公开(公告)号：US20100164526A1

公开(公告)日：2010-07-01

申请号：US12649109

申请日：2009-12-29

Applicant: Alberto Pagani

Inventor： Alberto Pagani

IPC: G01R31/02 ,  G01R1/06

CPC classification number: G01R1/06716 ,  G01R1/06727 ,  G01R1/06733

Abstract: A MEMS probe adapted to contact a corresponding terminal of an integrated circuit, integrated on at least one chip of a semiconductor material wafer during a test phase of the wafer is provided. The probe includes a support structure comprising a first access terminal and a second access terminal; the support structure defines a conductive path between said first access terminal and said second access terminal. The probes further-includes a probe region connected to the support structure adapted to contact the corresponding terminal of the integrated circuit during the test phase for providing at least one test signal received from the first access terminal and the second access terminal to the integrated circuit through at least one portion of the conductive path, and/or providing at least one test signal generated by the integrated circuit to at least one between the first access terminal and the second access terminal trough at least one portion of the conductive path. The probe region is arranged on the conductive path of the support structure between said first access terminal and said second access terminal.

Abstract translation: 提供一种MEMS探针，其适于在晶片的测试阶段期间与集成在半导体材料晶片的至少一个芯片上的集成电路的相应端子接触。 探针包括支撑结构，该支撑结构包括第一接入终端和第二接入终端; 所述支撑结构限定所述第一接入终端与所述第二接入终端之间的导电路径。 所述探头进一步包括连接到所述支撑结构的探针区域，所述探测区域在所述测试阶段期间与所述集成电路的相应端子接触，以便从所述第一接入终端接收的至少一个测试信号和所述第二接入终端通过 所述导电路径的至少一部分，和/或将由所述集成电路产生的至少一个测试信号提供给所述第一接入终端和所述第二接入终端之间的至少一个在所述导电路径的至少一部分。 探针区域布置在所述第一接入终端和所述第二接入终端之间的支撑结构的导电路径上。

公开(公告)号：US20100006856A1

公开(公告)日：2010-01-14

申请号：US12564719

申请日：2009-09-22

Applicant: Salvatore LEONARDI ,  Claudia Caligiore

Inventor： Salvatore LEONARDI ,  Claudia Caligiore

IPC: H01L33/00 ,  H01L27/12

CPC classification number: H01L21/02686 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1229 ,  H01L27/1281 ,  H01L29/66757

Abstract: A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.

Abstract translation: 一种薄膜晶体管器件的制造方法，其特征在于，在基板上形成介电绝缘层，在所述绝缘层上形成非晶硅层，使所述非晶硅层结晶化，得到多晶硅，在所述多晶硅上形成栅极结构 硅，并且相对于栅极结构横向地在多晶硅内形成第一掺杂区域。 所述结晶步骤包括在所述非晶硅层上形成第一覆盖电介质区域，然后使用激光照射所述非晶硅层，以便形成由所述第一覆盖电介质区域下方的非晶硅的分离部分分离的多晶硅的有源区域。

公开(公告)号：US20090154558A1

公开(公告)日：2009-06-18

申请号：US12275947

申请日：2008-11-21

Applicant: Megha Agarwal ,  Sumit Johar ,  Saha Kaushik ,  Emiliano Mario Piccinelli

Inventor： Megha Agarwal ,  Sumit Johar ,  Saha Kaushik ,  Emiliano Mario Piccinelli

IPC: H04N7/26

CPC classification number: H04N19/40 ,  H04N19/115 ,  H04N19/149 ,  H04N19/196 ,  H04N19/61

Abstract: Rate control algorithms are adapted to cover multiple encoding standards are described. A rate controller includes an input adaptation interface, a core rate controller, and an output adaptation interface. The input adaptation interface converts rate control input parameters of a target encoding standard to corresponding native control input parameters of the rate controller. The core rate controller is coupled to the output of the input adaptation interface generating output parameters conforming to its native encoding standard. The output adaptation interface is coupled to the output of the core rate controller converting the generated output parameters to equivalent rate control output parameters conforming to the target encoding standard.

Abstract translation: 速率控制算法适用于覆盖多种编码标准。 速率控制器包括输入适配接口，核心速率控制器和输出适配接口。 输入自适应接口将目标编码标准的速率控制输入参数转换为速率控制器的相应本机控制输入参数。 核心速率控制器耦合到输入自适应接口的输出，产生符合其天然编码标准的输出参数。 输出适配接口耦合到核心速率控制器的输出，将所生成的输出参数转换为符合目标编码标准的等效速率控制输出参数。

公开(公告)号：US20090103622A1

公开(公告)日：2009-04-23

申请号：US12253062

申请日：2008-10-16

Applicant: Subarna Tripathi ,  Kaushik Saha ,  Emiliana Picinelli

Inventor： Subarna Tripathi ,  Kaushik Saha ,  Emiliana Picinelli

IPC: H04N7/26

CPC classification number: H04N19/59 ,  H04N19/103 ,  H04N19/176 ,  H04N19/196 ,  H04N19/40

Abstract: A system and corresponding method determines a macroblock partition to transcode digital data from a first video standard to a second video standard with any spatial resolution. The system includes a processing module and an encoding module. The processing module processes digital data to determine a macroblock partition. The encoding module is coupled to the processing module for encoding the digital data based on the macroblock partition. The system is further coupled to a decoding module for receiving the digital data. The method determines the partition of a macroblock for transcoding digital data with any spatial resolution and without any motion estimation.

Abstract translation: 系统和相应的方法确定宏块分区以将数字数据从第一视频标准转码为具有任何空间分辨率的第二视频标准。 该系统包括处理模块和编码模块。 处理模块处理数字数据以确定宏块分区。 编码模块耦合到处理模块，用于基于宏块分区对数字数据进行编码。 该系统进一步耦合到用于接收数字数据的解码模块。 该方法确定用于使用任何空间分辨率对数字数据进行代码转换并且没有任何运动估计的宏块的分区。

公开(公告)号：US20080292934A1

公开(公告)日：2008-11-27

申请号：US12126082

申请日：2008-05-23

Applicant: Raffaele Vecchione ,  Salvatore Leonardi ,  Giuseppe Mensitieri ,  Anna Borriello

Inventor： Raffaele Vecchione ,  Salvatore Leonardi ,  Giuseppe Mensitieri ,  Anna Borriello

IPC: H01M8/10 ,  H01B1/12

CPC classification number: H01B1/124 ,  H01B1/04 ,  H01M4/921 ,  H01M4/926 ,  H01M8/0289 ,  H01M8/1004 ,  H01M8/1007 ,  H01M2008/1095 ,  Y02E60/521 ,  Y02P70/56

Abstract: A composite product is for an electrode of a fuel cell including a catalyst, an electrically conductive phase which supports such catalyst, a protonically conductive phase, and a porous phase. At least the contact between the catalyst and the electrically and protonically conductive phases, and preferably also the contact of the porous phase with the catalyst and with the electrically and protonically conductive phases, is improved or maximized. Each of the phases is individually continuous, and such phases are continuous with each other.

Abstract translation: 复合产品用于包括催化剂，支持这种催化剂的导电相，质子导电相和多孔相的燃料电池的电极。 至少催化剂与电和质子导电相之间的接触，以及优选多孔相与催化剂以及电和质子导电相的接触被改善或最大化。 每个相是单独连续的，并且这些相是彼此连续的。

公开(公告)号：US20080211701A1

公开(公告)日：2008-09-04

申请号：US12060809

申请日：2008-04-01

Applicant: Francesco Pappalardo ,  Giuseppe Notarangelo

Inventor： Francesco Pappalardo ,  Giuseppe Notarangelo

IPC: H03M7/00

CPC classification number: G06F13/4072 ,  G06F13/4213

Abstract: Digital signals are transmitted on a bus at given instants selectively in a non-encoded format and an encoded format. The decision whether to transmit the signals in non-encoded format or in encoded format is taken in part, based on a comparison of the signal to be transmitted on the bus for an instant of the aforesaid given instants with the signal transmitter on the bus for the preceding instant, so as to minimize switching activity on the bus.

Abstract translation: 数字信号在给定时刻的总线上以非编码格式和编码格式有选择地发送。 基于在上述给定时刻的总线上发送的信号与总线上的信号发送器的比较，部分地采用以非编码格式或编码格式发送信号的决定 在前一时刻，以便最小化总线上的开关活动。

公开(公告)号：US20080189557A1

公开(公告)日：2008-08-07

申请号：US11336411

申请日：2006-01-19

Applicant: Francesco Pipitone ,  Francesco Tomaiuolo ,  Marco Messina ,  Alessandro Raimondo ,  Vijay Malhi ,  Salvatore Giove

Inventor： Francesco Pipitone ,  Francesco Tomaiuolo ,  Marco Messina ,  Alessandro Raimondo ,  Vijay Malhi ,  Salvatore Giove

IPC: G06F12/14 ,  H04L9/00

CPC classification number: G06F12/1425 ,  G06F21/79

Abstract: A memory device including at least one storage area for storing data and a protection control structure adapted to selectively allow an external device access to the at least one storage area of the memory, the storage area being not freely accessible by the external device if protected. The memory device further includes a control logic adapted to identify an access request by the external device to the at least one storage area and cooperating with the protection control structure for managing an unlock procedure for selectively granting the external device at least temporary access rights to the storage area if protected. The memory device further includes means for providing a first code to the external device in said unlock procedure, means for receiving a second code from the external device in response to said first code, and means for verifying validity of the received second code, wherein said means for verifying validity are adapted to ascertain a correspondence of the second code with the first code based on a predetermined relationship. Said control logic instructs the protection control structure to grant access to the storage area if the validity of the received second code has been verified.

Abstract translation: 一种包括用于存储数据的至少一个存储区域和适于选择性地允许外部设备访问存储器的至少一个存储区域的保护控制结构的存储设备，如果被保护，则该外部设备不能自由访问该存储区域。 该存储装置还包括控制逻辑，该控制逻辑适于将该外部设备的访问请求识别至该至少一个存储区域，并与该保护控制结构协作以管理解锁过程，用于选择性地授予该外部设备至少对该外部设备的临时访问权限 保存区域。 存储装置还包括用于在所述解锁过程中向外部设备提供第一代码的装置，用于响应于所述第一代码从外部设备接收第二代码的装置以及用于验证接收到的第二代码的有效性的装置，其中所述 用于验证有效性的装置适于基于预定关系确定第二代码与第一代码的对应关系。 如果所接收的第二代码的有效性已被验证，则所述控制逻辑指示保护控制结构向存储区域授予访问权限。

公开(公告)号：US20080155365A1

公开(公告)日：2008-06-26

申请号：US11963036

申请日：2007-12-21

Applicant: Marco Casarsa

Inventor： Marco Casarsa

IPC: G01R31/3181 ,  G06F11/26

CPC classification number: G01R31/318541

Abstract: A scan chain architecture includes a cascade of flip-flop cells each having at least one input and output or an inverted output. The output or inverted output of a flip-flop is connected to the input of the subsequent flip-flop. The connection between two consecutive flip-flops of the scan chain is selected according to the status of a given flip-flop cell, the status of a previous cell, and the status of the connection between these cells.

Abstract translation: 扫描链架构包括每个具有至少一个输入和输出或反相输出的触发器单元级联。 触发器的输出或反相输出连接到后续触发器的输入端。 根据给定的触发器单元的状态，先前小区的状态以及这些小区之间的连接的状态来选择扫描链的两个连续的触发器之间的连接。