公开(公告)号：US07710772B2

公开(公告)日：2010-05-04

申请号：US12109525

申请日：2008-04-25

申请人： Alessandro Magnavacca ,  Francesco Pipitone ,  Carlo Lisi ,  Antonio Geraci

发明人： Alessandro Magnavacca ,  Francesco Pipitone ,  Carlo Lisi ,  Antonio Geraci

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10

摘要： A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels.

摘要翻译： 存储器具有被组织成单词页面的k级单元阵列，每个存储一串位。 存储装置包括输入了N位串的编码电路，并产生相应的k级串。 输入有k级串的程序电路，以存储具有k级的c个单元的组。 读取电路读取存储在具有k个级别的c个单元组中的数据，并生成k级字符串。 输入读取解码电路，其具有从具有k个级别的c个单元的组读取的k级字符串，以生成N位串。 每个页面的字被分组成单词组，每个单词包括具有k个级别的c单元的组，以及存储该单词的至少一个剩余位，以及该页面中的其他单词的相应剩余位， c细胞与k水平。

公开(公告)号：US20080266946A1

公开(公告)日：2008-10-30

申请号：US12109525

申请日：2008-04-25

申请人： Alessandro Magnavacca ,  Francesco Pipitone ,  Carlo Lisi ,  Antonino Geraci

发明人： Alessandro Magnavacca ,  Francesco Pipitone ,  Carlo Lisi ,  Antonino Geraci

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10

摘要： A memory has an array of k-level cells, organized into pages of words, each storing a string of bits. The memory device includes a coding circuit input with strings of N bits, and generates corresponding k-level strings. A program circuit is input with the k-level strings to stores in groups of c cells with k levels. A read circuit reads data stored in groups of c cells with k levels and generates k-level strings. A read decoding circuit is input with k-level strings read from groups of c cells with k levels to generate strings of N bits. The words of each page are grouped in groups of words, each word including groups of c cells with k levels, and at least one remaining bit of the word being stored, with corresponding remaining bits of other words of the page, in a group of c cells with k levels.

摘要翻译： 存储器具有被组织成单词页面的k级单元阵列，每个存储一串位。 存储装置包括输入了N位串的编码电路，并产生相应的k级串。 输入有k级串的程序电路，以存储具有k级的c个单元的组。 读取电路读取存储在具有k个级别的c个单元组中的数据，并生成k级字符串。 输入读取解码电路，其具有从具有k个级别的c个单元的组读取的k级字符串，以生成N位串。 每个页面的字被分组成单词组，每个单词包括具有k个级别的c单元的组，以及存储该单词的至少一个剩余位，以及该页面中的其他单词的相应剩余位， c细胞与k水平。

公开(公告)号：US20080189557A1

公开(公告)日：2008-08-07

申请号：US11336411

申请日：2006-01-19

申请人： Francesco Pipitone ,  Francesco Tomaiuolo ,  Marco Messina ,  Alessandro Raimondo ,  Vijay Malhi ,  Salvatore Giove

发明人： Francesco Pipitone ,  Francesco Tomaiuolo ,  Marco Messina ,  Alessandro Raimondo ,  Vijay Malhi ,  Salvatore Giove

IPC分类号： G06F12/14 ,  H04L9/00

CPC分类号： G06F12/1425 ,  G06F21/79

摘要： A memory device including at least one storage area for storing data and a protection control structure adapted to selectively allow an external device access to the at least one storage area of the memory, the storage area being not freely accessible by the external device if protected. The memory device further includes a control logic adapted to identify an access request by the external device to the at least one storage area and cooperating with the protection control structure for managing an unlock procedure for selectively granting the external device at least temporary access rights to the storage area if protected. The memory device further includes means for providing a first code to the external device in said unlock procedure, means for receiving a second code from the external device in response to said first code, and means for verifying validity of the received second code, wherein said means for verifying validity are adapted to ascertain a correspondence of the second code with the first code based on a predetermined relationship. Said control logic instructs the protection control structure to grant access to the storage area if the validity of the received second code has been verified.

摘要翻译： 一种包括用于存储数据的至少一个存储区域和适于选择性地允许外部设备访问存储器的至少一个存储区域的保护控制结构的存储设备，如果被保护，则该外部设备不能自由访问该存储区域。 该存储装置还包括控制逻辑，该控制逻辑适于将该外部设备的访问请求识别至该至少一个存储区域，并与该保护控制结构协作以管理解锁过程，用于选择性地授予该外部设备至少对该外部设备的临时访问权限 保存区域。 存储装置还包括用于在所述解锁过程中向外部设备提供第一代码的装置，用于响应于所述第一代码从外部设备接收第二代码的装置以及用于验证接收到的第二代码的有效性的装置，其中所述 用于验证有效性的装置适于基于预定关系确定第二代码与第一代码的对应关系。 如果所接收的第二代码的有效性已被验证，则所述控制逻辑指示保护控制结构向存储区域授予访问权限。

公开(公告)号：US07050343B2

公开(公告)日：2006-05-23

申请号：US10789443

申请日：2004-02-27

申请人： Promod Kumar ,  Francesco Tomaiuolo ,  Pierpaolo Nicosia ,  Luca Giuseppe De Ambroggi ,  Francesco Pipitone

发明人： Promod Kumar ,  Francesco Tomaiuolo ,  Pierpaolo Nicosia ,  Luca Giuseppe De Ambroggi ,  Francesco Pipitone

IPC分类号： G11C29/00

CPC分类号： G11C29/16 ,  G11C16/04 ,  G11C2029/0401 ,  G11C2029/0405

摘要： An Electric Wafer Sort (EWS) flow is implemented by expanding the functions of the micro-controller embedded in a FLASH EPROM memory device and of the integrated test structures. Test routines are executed by the onboard micro-controllers (that may be reading either from an embedded ROM or from a GLOBAL CACHE provided) internally without involving any external complex or expensive test equipment to control the test program. The device architecture is transparent from a tester point of view, with a standard interface having a set of defined commands and instructions to be interpreted by the on board microcontroller and internally executed.

摘要翻译： 通过扩展嵌入在FLASH EPROM存储器件和集成测试结构中的微控制器的功能来实现电晶片分级（EWS）流程。 测试例程由内部微控制器（可能是从嵌入式ROM或提供的GLOBAL CACHE提供）内部执行，而不涉及任何外部复杂或昂贵的测试设备来控制测试程序。 从测试人员的角度来看，器件架构是透明的，标准接口具有一组定义的命令和指令，由板上微控制器解释并在内部执行。

公开(公告)号：US06801466B2

公开(公告)日：2004-10-05

申请号：US10331147

申请日：2002-12-27

申请人： Salvatore Giove ,  Luca De Ambroggi ,  Salvatore Nicosia ,  Francesco Tomaiulo ,  Kumar Promod ,  Giuseppe Piazza ,  Francesco Pipitone

发明人： Salvatore Giove ,  Luca De Ambroggi ,  Salvatore Nicosia ,  Francesco Tomaiulo ,  Kumar Promod ,  Giuseppe Piazza ,  Francesco Pipitone

IPC分类号： G11C702

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C16/28

摘要： A circuit for controlling a reference node in a sense amplifier switchable between an operating mode and a stand-by mode is provided. The reference node provides a reference voltage in the operating mode. The circuit may include circuitry for bringing the reference node to a starting voltage upon entry into the stand-by mode, circuitry for keeping the reference node at a pre-charging voltage in the stand-by mode, and circuitry for providing a comparison voltage closer to the pre-charging voltage than the starting voltage. Pulling circuitry may also be included for pulling the reference node toward a power supply voltage. Further, a controller may activate the pulling circuitry upon entering the stand-by mode, and disable the pulling circuitry when the voltage at the reference node reaches the comparison voltage.

摘要翻译： 提供了一种用于控制在操作模式和待机模式之间切换的读出放大器中的参考节点的电路。 参考节点在工作模式下提供参考电压。 电路可以包括用于在进入待机模式时使参考节点进入起始电压的电路，用于将参考节点保持在备用模式下的预充电电压的电路，以及用于提供比较电压更接近的电路 到预充电电压比启动电压。 还可以包括牵引电路以将参考节点拉向电源电压。 此外，控制器可以在进入待机模式时激活拉电路，并且当参考节点处的电压达到比较电压时禁止拉电路。