Method of manufacturing inkjet print head
    161.
    发明授权
    Method of manufacturing inkjet print head 有权
    制造喷墨打印头的方法

    公开(公告)号:US07856717B2

    公开(公告)日:2010-12-28

    申请号:US12033222

    申请日:2008-02-19

    Abstract: A method of manufacturing an inkjet print head simplifies a manufacturing process and uniformly forms an ink channel and includes forming a chamber layer using a low-speed optical hardening material on a substrate, hardening regions of the chamber layer for the wall of an ink channel by selectively exposing the chamber layer to light, forming a nozzle layer using a high-speed optical hardening material, having a higher optical reaction speed than that of the low-speed optical hardening material, on the chamber layer, hardening regions of the nozzle layer other than nozzles by selectively exposing the nozzle layer to light, and forming the ink channel and the nozzles by developing the chamber layer and the non-exposed regions of the nozzle layer.

    Abstract translation: 一种制造喷墨打印头的方法简化了制造过程,并且均匀地形成油墨通道,并且包括在基板上使用低速光硬化材料形成室层,通过以下方式固化用于油墨通道壁的室层的区域: 选择性地将室层曝光,使用具有比低速光硬化材料更高的光学反应速度的高速光学硬化材料在腔室层上形成喷嘴层,其它喷嘴层的硬化区域 比喷嘴通过选择性地将喷嘴层暴露于光,并且通过显影喷涂层的室层和未曝光区域来形成油墨通道和喷嘴。

    Semiconductor device with reduced standby failures
    162.
    发明授权
    Semiconductor device with reduced standby failures 有权
    具有减少待机故障的半导体器件

    公开(公告)号:US07839717B2

    公开(公告)日:2010-11-23

    申请号:US12235812

    申请日:2008-09-23

    CPC classification number: G11C5/14

    Abstract: A semiconductor memory device includes a cell core storing data, a plurality of peripheral circuit components, collectively driving data to/from the cell core and providing a default state at an output signal state during an initialization process upon power-up, and an initialization circuit detecting a standby mode of operation for the semiconductor memory device, and upon detecting the standby mode controlling operation of the plurality of peripheral circuit components to provide the default state as the signal state during standby mode.

    Abstract translation: 半导体存储器件包括:存储数据的单元核心,多个外围电路部件,共同地向单元核心驱动数据,并且在上电时的初始化处理期间以输出信号状态提供默认状态;以及初始化电路 检测半导体存储器件的待机操作模式,并且在检测到多个外围电路组件的待机模式控制操作时提供默认状态作为待机模式期间的信号状态。

    LIGHT EMITTING DEVICE
    163.
    发明申请
    LIGHT EMITTING DEVICE 审中-公开
    发光装置

    公开(公告)号:US20100224854A1

    公开(公告)日:2010-09-09

    申请号:US12569435

    申请日:2009-09-29

    CPC classification number: H01L33/20 H01L2933/0083

    Abstract: A light emitting device (LED) is provided. The LED comprises a light emitting structure and a mixed-period photonic crystal structure. The light emitting structure comprises a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer. The mixed-period photonic crystal structure is on the light emitting structure.

    Abstract translation: 提供发光器件(LED)。 LED包括发光结构和混合周期光子晶体结构。 发光结构包括第一导电类型半导体层,有源层和第二导电类型半导体层。 混合周期光子晶体结构在发光结构上。

    SYSTEM AND METHOD FOR PROVIDING DEVICE MANAGEMENT SERVICE TO ELECTRONIC DEVICE HAVING NO BROADBAND COMMUNICATION MODULE
    164.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING DEVICE MANAGEMENT SERVICE TO ELECTRONIC DEVICE HAVING NO BROADBAND COMMUNICATION MODULE 审中-公开
    向没有宽带通信模块的电子设备提供设备管理服务的系统和方法

    公开(公告)号:US20100199333A1

    公开(公告)日:2010-08-05

    申请号:US12669756

    申请日:2008-07-18

    CPC classification number: H04L41/00 H04L41/046

    Abstract: Disclosed is a system for providing an electronic device with a DM service, including: a DM server for providing the electronic device with the DM service; and a wireless terminal capable of being directly connected to the DM server for establishing a DM session while cooperating with the electronic device, generating an MO used for managing the electronic device with reference to a DDF of the electronic device if the wireless terminal receives the DDF of the electronic device from the electronic device through the DM session, and transmitting the generated MO to the DM server.

    Abstract translation: 公开了一种用于向电子设备提供DM服务的系统,包括:DM服务器,用于向电子设备提供DM服务; 以及能够直接连接到DM服务器的无线终端,用于与电子设备协作建立DM会话,如果无线终端接收到DDF,则参照电子设备的DDF生成用于管理电子设备的MO 通过DM会话从电子设备发送电子设备,并将生成的MO发送到DM服务器。

    Apparatus for data aggregation using zone scheduling in wireless sensor network and method thereof
    165.
    发明授权
    Apparatus for data aggregation using zone scheduling in wireless sensor network and method thereof 有权
    用于无线传感器网络中的区域调度的数据聚合装置及其方法

    公开(公告)号:US07733809B2

    公开(公告)日:2010-06-08

    申请号:US11892474

    申请日:2007-08-23

    CPC classification number: H04L12/66

    Abstract: A data aggregation method and data aggregation apparatus are provided. More particularly the data aggregation method includes: generating a plurality of data aggregation trees according to connection relationships between clusters that constitute a sensor network using a geographical code (GGC), selecting a single activation zone for each of the clusters which configures each of the plurality of data aggregation trees, selecting a maximum energy tree having a maximum total residual energy from the plurality of data aggregation trees, based on the single activation zone, and generating a tree list including activation zone information which corresponds to the maximum energy tree, and information about the maximum energy tree.

    Abstract translation: 提供了一种数据聚合方法和数据聚合装置。 更具体地,数据聚合方法包括:根据构成使用地理码(GGC)的传感器网络的集群之间的连接关系生成多个数据聚合树,为配置每个多个集群的每个集群选择单个激活区域 的数据聚合树,基于单个激活区域选择具有来自多个数据聚合树的最大总剩余能量的最大能量树,并且生成包括对应于最大能量树的激活区域信息的树列表和信息 关于最大能量树。

    FLASH MEMORY DEVICE CAPABLE OF REDUCED PROGRAMMING TIME
    167.
    发明申请
    FLASH MEMORY DEVICE CAPABLE OF REDUCED PROGRAMMING TIME 失效
    具有减少编程时间的闪存存储器件

    公开(公告)号:US20100067303A1

    公开(公告)日:2010-03-18

    申请号:US12620758

    申请日:2009-11-18

    CPC classification number: G11C16/3404

    Abstract: A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

    Abstract translation: 提供了一种闪存器件,其包括适于将具有目标电压的编程电压提供给所选字线的高压发生器电路。 闪存器件适于根据在降低到目标电压之后的程序电压恢复到目标电压时终止编程间隔。 还提供了一种用于操作闪速存储器件的方法。

    INKJET PRINTHEAD AND METHOD OF MANUFACTURING THE SAME
    168.
    发明申请
    INKJET PRINTHEAD AND METHOD OF MANUFACTURING THE SAME 有权
    喷墨打印机及其制造方法

    公开(公告)号:US20100060695A1

    公开(公告)日:2010-03-11

    申请号:US12468884

    申请日:2009-05-20

    CPC classification number: B41J2/1603 B41J2/1631 B41J2/1639

    Abstract: An inkjet printhead includes: a substrate in which an ink feed hole is formed; a chamber layer which is formed on the substrate by performing a photolithography process and which includes a first photosensitive resin; and a nozzle layer which is formed on the chamber layer by performing a photolithography process and which includes a second photosensitive resin. The first photosensitive resin and the second photosensitive resin are materials which are developed by different developing solutions, respectively. Additional layers and components may be incorporated into the inkjet printhead and may be formed on an upper surface of the substrate. The additional layers and components may include an insulating layer, one or more heaters, one or more electrodes, a passivation layer, a glue layer, and an anti-cavitation layer.

    Abstract translation: 喷墨打印头包括:形成有供墨孔的基板; 通过进行光刻工艺在基板上形成的包括第一感光性树脂的室层; 以及通过进行光刻工艺在腔室层上形成并包括第二感光树脂的喷嘴层。 第一感光性树脂和第二感光性树脂是分别通过不同的显影液显影的材料。 另外的层和组件可以结合到喷墨打印头中,并且可以形成在基板的上表面上。 附加层和部件可以包括绝缘层,一个或多个加热器,一个或多个电极,钝化层,胶层和抗空穴层。

    Circuit and method generating program voltage for non-volatile memory device
    169.
    发明授权
    Circuit and method generating program voltage for non-volatile memory device 有权
    用于非易失性存储器件的电路和方法产生编程电压

    公开(公告)号:US07646639B2

    公开(公告)日:2010-01-12

    申请号:US11844514

    申请日:2007-08-24

    CPC classification number: G11C16/12 G11C16/0483

    Abstract: Provided are a circuit and method for generating a program voltage, and a non-volatile memory device using the same. The circuit, which generates a program voltage for programming a memory cell of a semiconductor memory device, includes a program voltage controller and a voltage generating unit. The program voltage controller generates a program voltage control signal according to program/erase operations information. The voltage controller generates a program voltage in response to the program voltage control signal.

    Abstract translation: 提供了用于产生编程电压的电路和方法,以及使用其的非易失性存储器件。 产生用于对半导体存储器件的存储单元进行编程的编程电压的电路包括编程电压控制器和电压产生单元。 程序电压控制器根据编程/擦除操作信息产生编程电压控制信号。 电压控制器响应于编程电压控制信号产生编程电压。

    Flash memory device capable of improving reliability
    170.
    发明授权
    Flash memory device capable of improving reliability 有权
    能够提高可靠性的闪存装置

    公开(公告)号:US07558114B2

    公开(公告)日:2009-07-07

    申请号:US11454481

    申请日:2006-06-16

    CPC classification number: G11C16/3418 G11C16/26 G11C16/3427

    Abstract: A flash memory device includes a memory cell array having a first region and a second region that include memory cells arranged in a plurality of rows and columns; an address storage circuit adapted to store address information for defining the second region; a row decoder circuit adapted to select one of the first and second regions in response to an external address; a voltage generating circuit adapted to generate a read voltage to be provided to a row of the selected region by the row decoder circuit during a read operation; a detecting circuit adapted to detect whether the selected region is included in the second region on the basis of address information and external address information that are stored in the address storage circuit; and a control logic adapted to control the voltage generating circuit in response to an output of the detecting circuit during the read operation. The control logic controls the voltage generating circuit so that a read voltage provided to the row of the second region is lower than a read voltage provided to a row of the first region.

    Abstract translation: 闪速存储器件包括具有第一区域和第二区域的存储单元阵列,所述第二区域包括排列成多行和列的存储单元; 地址存储电路,适于存储用于定义第二区域的地址信息; 行解码器电路,其适于响应于外部地址来选择所述第一和第二区域中的一个; 电压发生电路,其适于在读取操作期间由行解码器电路产生要提供给所选区域的行的读取电压; 检测电路,其适于基于存储在所述地址存储电路中的地址信息和外部地址信息来检测所述选择区域是否包括在所述第二区域中; 以及控制逻辑,适于在读取操作期间响应于检测电路的输出来控制电压产生电路。 控制逻辑控制电压产生电路,使得提供给第二区域的行的读取电压低于提供给第一区域的行的读取电压。

Patent Agency Ranking