公开(公告)号：US07839717B2

公开(公告)日：2010-11-23

申请号：US12235812

申请日：2008-09-23

申请人： Jin-wook Lee ,  Jin-yub Lee

发明人： Jin-wook Lee ,  Jin-yub Lee

IPC分类号： G11C8/18

CPC分类号： G11C5/14

摘要： A semiconductor memory device includes a cell core storing data, a plurality of peripheral circuit components, collectively driving data to/from the cell core and providing a default state at an output signal state during an initialization process upon power-up, and an initialization circuit detecting a standby mode of operation for the semiconductor memory device, and upon detecting the standby mode controlling operation of the plurality of peripheral circuit components to provide the default state as the signal state during standby mode.

摘要翻译： 半导体存储器件包括：存储数据的单元核心，多个外围电路部件，共同地向单元核心驱动数据，并且在上电时的初始化处理期间以输出信号状态提供默认状态;以及初始化电路 检测半导体存储器件的待机操作模式，并且在检测到多个外围电路组件的待机模式控制操作时提供默认状态作为待机模式期间的信号状态。

公开(公告)号：US07907454B2

公开(公告)日：2011-03-15

申请号：US12247288

申请日：2008-10-08

申请人： Min-Gun Park ,  Jin-yub Lee

发明人： Min-Gun Park ,  Jin-yub Lee

IPC分类号： G11C16/06

CPC分类号： G11C16/3454 ,  G11C16/0483

摘要： A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect to a selected memory cell in the memory string. The method includes applying a voltage, obtained by adding a threshold voltage of the string selection transistor to a power supply voltage, to a string selection line connected to the string selection transistor; applying a ground voltage to wordlines connected to each of the memory cells and a ground selection line connected to the ground selection transistor; precharging a bitline connected to the memory string to the power supply voltage; and determining whether a programming operation of the selected memory cell is complete.

摘要翻译： 提供了一种用于验证闪存设备的编程操作的方法。 闪速存储器件包括串联选择晶体管，多个存储单元和地选择晶体管串联连接的至少一个存储器串，并且相对于存储器串中的所选存储单元执行编程操作。 该方法包括将串联选择晶体管的阈值电压加到电源电压而获得的电压施加到连接到串选择晶体管的串选择线; 对连接到每个存储单元的字线和连接到地选择晶体管的接地选择线施加接地电压; 将连接到存储器串的位线预充电到电源电压; 以及确定所选存储单元的编程操作是否完成。

公开(公告)号：US07511509B2

公开(公告)日：2009-03-31

申请号：US11605224

申请日：2006-11-29

申请人： You-sang Lee ,  Jin-yub Lee

发明人： You-sang Lee ,  Jin-yub Lee

IPC分类号： G01R31/02

CPC分类号： G01R31/318566

摘要： A semiconductor device includes a plurality of fuses, and a plurality of latch circuits respectively electrically connected to the plurality of fuses. The plurality of latch circuits are configured to store respective fuse-cut information from the plurality of fuses, and to then sequentially transmit the fuse-cut information through the latch circuits to output sequential data indicative of a fuse-cut state of the plurality of fuses.

摘要翻译： 半导体器件包括多个保险丝，以及分别电连接到多个保险丝的多个锁存电路。 多个锁存电路被配置为存储来自多个保险丝的相应熔丝切断信息，然后通过锁存电路顺序地发送熔丝切断信息，以输出表示多个保险丝的熔丝切断状态的顺序数据 。

公开(公告)号：US20080101122A1

公开(公告)日：2008-05-01

申请号：US11635995

申请日：2006-12-08

申请人： Hyung-seok Kang ,  Eui-gyu Han ,  Gyeong-soo Han ,  Jin-yub Lee ,  Hoo-sung Kim

发明人： Hyung-seok Kang ,  Eui-gyu Han ,  Gyeong-soo Han ,  Jin-yub Lee ,  Hoo-sung Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.

摘要翻译： 提供了一种提高闪存阵列的读取干扰特性的方法。 根据该方法，在具有串联选择晶体管，多个存储单元和接地选择晶体管的至少一个单元串的闪速存储器阵列中，将第一读取电压施加到连接的串选择线 到串选择晶体管的栅极和连接到接地选择晶体管的栅极的接地选择线。 将接地电压施加到从存储单元中选择的存储单元的字线。 第二读取电压被施加到与串选择晶体管和地选择晶体管相邻的未被选择的存储单元中的存储单元的字线。 然后，将第一读取电压施加到未被选择的其他存储单元。 第二读取电压低于第一读取电压。

公开(公告)号：US20070136563A1

公开(公告)日：2007-06-14

申请号：US11424575

申请日：2006-06-16

申请人： Min-gun Park ,  Jin-yub Lee

发明人： Min-gun Park ,  Jin-yub Lee

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G11C16/34

摘要： Some embodiments of the present invention provide programming operations for reducing a program time for a nonvolatile memory device. A nonvolatile semiconductor memory device is programmed by receiving data to be programmed into memory cells from a host, programming the data into the memory cells, performing a verify read operation to determine whether the data has been successfully programmed into the memory cells, and performing a Y-scan operation while performing the verify read operation to sequentially scan and output data read from bit lines coupled to the memory cells.

摘要翻译： 本发明的一些实施例提供了用于减少非易失性存储器件的编程时间的编程操作。 通过从主机接收要编程到存储器单元中的数据来编程非易失性半导体存储器件，将数据编程到存储器单元中，执行验证读取操作以确定数据是否被成功编程到存储器单元中，以及执行 Y扫描操作，同时执行验证读取操作以顺序地扫描和输出从耦合到存储器单元的位线读取的数据。

公开(公告)号：US07949819B2

公开(公告)日：2011-05-24

申请号：US11978582

申请日：2007-10-30

申请人： Sang-chul Kang ,  Jin-yub Lee

发明人： Sang-chul Kang ,  Jin-yub Lee

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

CPC分类号： G11C16/08 ,  G11C16/20

摘要： According to an example embodiment, a method of changing a block size in a flash memory device having a multi-plane scheme may include decoding an external input address and changing the block size of the flash memory device from a first block size to a second block size. The external input address may be decoded into a block address and a page address. The block size of the flash memory device may be changed from the first block size to the second block size by shifting at least one bit of the block address to the page address or shifting at least one bit of the page address to the block address.

摘要翻译： 根据示例实施例，一种改变具有多平面方案的快闪存储器件中的块大小的方法可以包括解码外部输入地址并将闪存器件的块大小从第一块大小改变为第二块 尺寸。 外部输入地址可以被解码为块地址和页地址。 通过将块地址的至少一位移位到页地址或将页地址的至少一位移位到块地址，可以将闪速存储器件的块大小从第一块大小改变为第二块大小。

公开(公告)号：US07394700B2

公开(公告)日：2008-07-01

申请号：US11424575

申请日：2006-06-16

申请人： Min-gun Park ,  Jin-yub Lee

发明人： Min-gun Park ,  Jin-yub Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/34

摘要： Some embodiments of the present invention provide programming operations for reducing a program time for a nonvolatile memory device. A nonvolatile semiconductor memory device is programmed by receiving data to be programmed into memory cells from a host, programming the data into the memory cells, performing a verify read operation to determine whether the data has been successfully programmed into the memory cells, and performing a Y-scan operation while performing the verify read operation to sequentially scan and output data read from bit lines coupled to the memory cells.

摘要翻译： 本发明的一些实施例提供了用于减少非易失性存储器件的编程时间的编程操作。 通过从主机接收要编程到存储器单元中的数据来编程非易失性半导体存储器件，将数据编程到存储器单元中，执行验证读取操作以确定数据是否被成功编程到存储器单元中，以及执行 Y扫描操作，同时执行验证读取操作以顺序地扫描和输出从耦合到存储器单元的位线读取的数据。

公开(公告)号：US20090052252A1

公开(公告)日：2009-02-26

申请号：US12254205

申请日：2008-10-20

申请人： Hyung-seok Kang ,  Eui-gyu Han ,  Gyeong-soo Han ,  Jin-yub Lee ,  Hoo-sung Kim

发明人： Hyung-seok Kang ,  Eui-gyu Han ,  Gyeong-soo Han ,  Jin-yub Lee ,  Hoo-sung Kim

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/26

摘要： Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.

摘要翻译： 提供了一种提高闪存阵列的读取干扰特性的方法。 根据该方法，在具有串联选择晶体管，多个存储单元和接地选择晶体管的至少一个单元串的闪速存储器阵列中，将第一读取电压施加到连接的串选择线 到串选择晶体管的栅极和连接到接地选择晶体管的栅极的接地选择线。 将接地电压施加到从存储单元中选择的存储单元的字线。 第二读取电压被施加到与串选择晶体管和地选择晶体管相邻的未被选择的存储单元中的存储单元的字线。 然后，将第一读取电压施加到未被选择的其他存储单元。 第二读取电压低于第一读取电压。

公开(公告)号：US20080084768A1

公开(公告)日：2008-04-10

申请号：US11604692

申请日：2006-11-28

申请人： Dae-sik Park ,  Jin-yub Lee

发明人： Dae-sik Park ,  Jin-yub Lee

IPC分类号： G11C16/04 ,  G11C7/10 ,  G11C11/34

CPC分类号： G11C7/1078 ,  G11C7/1087 ,  G11C11/5628

摘要： A memory device and method thereof are provided. The example memory device may include a first buffer receiving most significant bit (MSB) data and least significant bit (LSB) data to be stored within a memory cell, a second buffer loading stored LSB data stored from the memory cell and a data loader generating at least one load signal based upon logic levels of the received MSB data from the first buffer and the loaded LSB data from the memory cell, the at least one load signal controlling programming permissions for the memory cell. The example method may include receiving LSB data, storing the received LSB data within a memory cell, receiving MSB data, loading the LSB data from the programmed memory cell, generating at least one load signal based upon logic levels of the received MSB data and the loaded LSB data, the at least one load signal controlling programming permissions for the memory cell and storing the MSB data within the memory cell based on the at least one load signal.

摘要翻译： 提供了一种存储器件及其方法。 该示例性存储器件可以包括接收要存储在存储器单元内的最高有效位（MSB）数据和最低有效位（LSB））数据的第一缓冲器，第二缓冲器加载从存储器单元存储的存储的LSB数据，以及数据加载器生成 基于来自第一缓冲器的接收到的MSB数据的逻辑电平和来自存储器单元的加载的LSB数据的至少一个负载信号，所述至少一个负载信号控制对存储器单元的编程许可。 示例性方法可以包括接收LSB数据，将接收的LSB数据存储在存储器单元内，接收MSB数据，从编程的存储器单元加载LSB数据，基于所接收的MSB数据的逻辑电平产生至少一个负载信号，以及 所述至少一个负载信号控制所述存储器单元的编程许可，并且基于所述至少一个负载信号将所述MSB数据存储在所述存储器单元内。

公开(公告)号：US07529127B2

公开(公告)日：2009-05-05

申请号：US11604692

申请日：2006-11-28

申请人： Dae-sik Park ,  Jin-yub Lee

发明人： Dae-sik Park ,  Jin-yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C7/1078 ,  G11C7/1087 ,  G11C11/5628

摘要： A memory device and method thereof are provided. The memory device may comprise a first buffer for receiving most significant bit (MSB) data and least significant bit (LSB) data to be stored within a memory cell; a second buffer for loading LSB data stored in the memory cell; and a data loader for generating at least one load signal based upon logic levels of the received MSB data in the first buffer and the loaded LSB data in the second buffer, the at least one load signal being configured to control programming permissions for the memory cell.

摘要翻译： 提供了一种存储器件及其方法。 存储器件可以包括用于接收要存储在存储器单元内的最高有效位（MSB）数据和最低有效位（LSB）数据的第一缓冲器; 用于加载存储在存储单元中的LSB数据的第二缓冲器; 以及数据加载器，用于基于所述第一缓冲器中接收的MSB数据的逻辑电平和所述第二缓冲器中加载的LSB数据来生成至少一个负载信号，所述至少一个负载信号被配置为控制所述存储器单元的编程许可 。