公开(公告)号：US10128236B2

公开(公告)日：2018-11-13

申请号：US15007882

申请日：2016-01-27

申请人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

发明人： Ji-Min Jeong ,  Kee-Sang Kwon ,  Jin-Wook Lee ,  Ki-Hyung Ko ,  Sang-Jine Park ,  Jae-Jik Baek ,  Bo-Un Yoon ,  Ji-Won Yun

IPC分类号： H01L29/772 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234

摘要： A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

公开(公告)号：USD820954S1

公开(公告)日：2018-06-19

申请号：US29599091

申请日：2017-03-31

申请人： Jin-Wook Lee

设计人： Jin-Wook Lee

公开(公告)号：US09911851B2

公开(公告)日：2018-03-06

申请号：US15079623

申请日：2016-03-24

申请人： Kang-Ill Seo ,  Jin-Wook Lee

发明人： Kang-Ill Seo ,  Jin-Wook Lee

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L23/485 ,  H01L21/8234

CPC分类号： H01L29/7851 ,  H01L21/823468 ,  H01L23/485 ,  H01L27/088 ,  H01L29/4983 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include a pair of spacers, which define a recess. The integrated circuit device may also include a lower conductive pattern in the recess and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern may have an etch selectivity with respect to the lower conductive pattern and may expose an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern. An inner sidewall of one of the pair of spacers, the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern may define a space and a capping pattern may be formed on the upper conductive pattern to seal a top portion of the space, such that a cavity is disposed under the capping pattern.

公开(公告)号：US20160358925A1

公开(公告)日：2016-12-08

申请号：US15084785

申请日：2016-03-30

申请人： Keun-hee BAI ,  Myeong-cheol KIM ,  Kwan-heum LEE ,  Do-hyoung KIM ,  Jin-wook LEE ,  Seung-mo HA ,  Dong-Hoon KHANG

发明人： Keun-hee BAI ,  Myeong-cheol KIM ,  Kwan-heum LEE ,  Do-hyoung KIM ,  Jin-wook LEE ,  Seung-mo HA ,  Dong-Hoon KHANG

IPC分类号： H01L27/11 ,  H01L27/088 ,  H01L21/308 ,  H01L27/02 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/1104 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

摘要： A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

摘要翻译： 半导体器件包括衬底，衬底上的鳍状有源区域图案，包括上部区域和下部区域的鳍状主动区域图案，围绕鳍状物区域图案的器件隔离层图案，在上部区域上的栅极图案 翅片有源区域图案和在翅片有源区域图案的下部区域上的应力器，其中，器件隔离层图案的顶表面比上部区域的顶表面低，并且高于下部区域的顶表面 。

公开(公告)号：US20160343858A1

公开(公告)日：2016-11-24

申请号：US14990863

申请日：2016-01-08

申请人： Yoon Hae KIM ,  Jin Wook LEE ,  Jong Ki JUNG ,  Myung II KANG ,  Kwang Yong YANG ,  Kwan Heum LEE ,  Byeong Chan LEE

发明人： Yoon Hae KIM ,  Jin Wook LEE ,  Jong Ki JUNG ,  Myung II KANG ,  Kwang Yong YANG ,  Kwan Heum LEE ,  Byeong Chan LEE

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165

CPC分类号： H01L21/823431 ,  H01L21/308 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor device includes a substrate having a first region and a second region, a plurality of first gate structures in the first region, the first gate structures being spaced apart from each other by a first distance, a plurality of second gate structures in the second region, the second gate structures being spaced apart from each other by a second distance, a first spacer on sidewalls of the first gate structures, a dielectric layer on the first spacer, a second spacer on sidewalls of the second gate structures, and a third spacer on the second spacer.

摘要翻译： 半导体器件包括具有第一区域和第二区域的衬底，第一区域中的多个第一栅极结构，第一栅极结构彼此间隔第一距离，第二栅极结构在第二区域中形成多个第二栅极结构 所述第二栅极结构彼此间隔开第二距离，所述第一栅极结构的侧壁上的第一间隔物，所述第一间隔物上的介电层，所述第二栅极结构的侧壁上的第二间隔物， 间隔物在第二间隔物上。

公开(公告)号：US20160133632A1

公开(公告)日：2016-05-12

申请号：US14853442

申请日：2015-09-14

申请人： Hong-bae PARK ,  Ja-hum KU ,  Myeong-cheol KIM ,  Jin-wook LEE ,  Sung-kee HAN

发明人： Hong-bae PARK ,  Ja-hum KU ,  Myeong-cheol KIM ,  Jin-wook LEE ,  Sung-kee HAN

IPC分类号： H01L27/11 ,  H01L27/02 ,  H01L27/092

CPC分类号： H01L27/1104 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

摘要： A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

摘要翻译： 一种方法包括在衬底上提供多个有源区，以及在所述多个有源区中的两个之间的至少第一器件隔离层，其中所述多个有源区在第一方向上延伸; 提供沿第二方向延伸的栅极层，所述栅极层形成多条栅极线，所述栅极线包括相对于彼此以直线延伸的第一栅极线和第二栅极线，所述第二栅极线和第二栅极线之间具有间隔，所述第一栅极 线和第二栅极线交叉有效区域中的至少一个，提供覆盖第一器件隔离层并围绕第一和第二栅极线周围的有源区域覆盖的绝缘层; 以及在所述第一栅极线和所述第二栅极线之间的空间中提供栅极间绝缘区域。

公开(公告)号：US09331072B2

公开(公告)日：2016-05-03

申请号：US14165721

申请日：2014-01-28

申请人： Kang-Ill Seo ,  Jin-Wook Lee

发明人： Kang-Ill Seo ,  Jin-Wook Lee

IPC分类号： H01L27/088 ,  H01L23/485 ,  H01L21/8234

CPC分类号： H01L29/7851 ,  H01L21/823468 ,  H01L23/485 ,  H01L27/088 ,  H01L29/4983 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include a pair of spacers, which define a recess. The integrated circuit device may also include a lower conductive pattern in the recess and an upper conductive pattern on the lower conductive pattern. The upper conductive pattern may have an etch selectivity with respect to the lower conductive pattern and may expose an upper surface of the lower conductive pattern adjacent a sidewall of the upper conductive pattern. An inner sidewall of one of the pair of spacers, the upper surface of the lower conductive pattern and the sidewall of the upper conductive pattern may define a space and a capping pattern may be formed on the upper conductive pattern to seal a top portion of the space, such that a cavity is disposed under the capping pattern.

摘要翻译： 提供具有空腔的集成电路器件和制造集成电路器件的方法。 集成电路器件可以包括限定凹部的一对间隔件。 集成电路器件还可以包括凹陷中的下导电图案和下导电图案上的上导电图案。 上导电图案可以具有相对于下导电图案的蚀刻选择性，并且可以暴露邻近上导电图案的侧壁的下导电图案的上表面。 一对间隔物中的一个的内侧壁，下导电图案的上表面和上导电图案的侧壁可以限定空间，并且可以在上导电图案上形成封盖图案，以密封上导电图案的顶部 空间，使得空腔设置在封盖图案下方。

公开(公告)号：US08928553B2

公开(公告)日：2015-01-06

申请号：US13273996

申请日：2011-10-14

申请人： Seong-Il Ham ,  Young-Ki Kim ,  Jin-Hyoung Kim ,  Shin-Il Kang ,  Jin-Wook Lee ,  Hyung-Jun Daniel Park ,  Yang-Un Lee

发明人： Seong-Il Ham ,  Young-Ki Kim ,  Jin-Hyoung Kim ,  Shin-Il Kang ,  Jin-Wook Lee ,  Hyung-Jun Daniel Park ,  Yang-Un Lee

IPC分类号： G09G5/00 ,  H04N21/41 ,  G06F3/14

CPC分类号： H04N21/4122 ,  G06F3/1423 ,  G06F3/1438 ,  G09G2356/00

摘要： A method and apparatus of a first device for selecting at least one of a plurality of second devices to be accessed. The method includes transmitting pieces of media data to the corresponding plurality of second devices one-to-one, and determining at least one of the plurality of second devices to be accessed by the first device according to a user's selection on the basis of the pieces of media data being reproduced by both the first device and each of the plurality of second devices.

摘要翻译： 一种用于选择待访问的多个第二设备中的至少一个的第一设备的方法和设备。 该方法包括：一对一地将多个媒体数据发送到对应的多个第二设备，以及根据用户的选择，根据第一设备确定第一设备要访问的至少一个第二设备 媒体数据由第一设备和多个第二设备中的每一个再现。

公开(公告)号：US08716117B2

公开(公告)日：2014-05-06

申请号：US13106977

申请日：2011-05-13

申请人： Myeongcheol Kim ,  Sooyeon Jeong ,  Joon Goo Hong ,  Dohyoung Kim ,  Yongjin Kim ,  Jin Wook Lee ,  Yoonhae Kim

发明人： Myeongcheol Kim ,  Sooyeon Jeong ,  Joon Goo Hong ,  Dohyoung Kim ,  Yongjin Kim ,  Jin Wook Lee ,  Yoonhae Kim

IPC分类号： H01L21/28

CPC分类号： H01L29/4966 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/66545

摘要： A semiconductor device and a method of forming the semiconductor device includes: forming gate electrodes on a semiconductor substrate and forming spacers on both side surfaces of the gate electrodes; forming capping patterns on the gate electrodes; and forming a metal contact between the gate electrodes. Each of the capping patterns is formed to have a width greater than a width of each of the gate electrodes.

摘要翻译： 半导体器件和形成半导体器件的方法包括：在半导体衬底上形成栅电极并在栅电极的两个侧表面上形成间隔物; 在栅电极上形成封盖图案; 以及在栅电极之间形成金属接触。 每个封盖图案形成为具有大于每个栅电极的宽度的宽度。

公开(公告)号：US08321765B2

公开(公告)日：2012-11-27

申请号：US12702481

申请日：2010-02-09

申请人： Jin-Wook Lee ,  Sang-Won Hwang

发明人： Jin-Wook Lee ,  Sang-Won Hwang

IPC分类号： G11C29/00

CPC分类号： G06F11/1068 ,  G11C16/26 ,  H03M13/15 ,  H03M13/1515 ,  H03M13/19

摘要： In a method of reading data from a non-volatile memory device, read data is generated based on a word line voltage. The read data includes data read from a plurality of sectors included in the non-volatile memory device. Bad sector data is transferred data based on read data and bad sector information. The bad sector data corresponds to data read from at least one bad sector included in the plurality of sectors. The bad sector information is updated by checking error bits of the bad sector data. The word line voltage is generated based on the updated bad sector information.

摘要翻译： 在从非易失性存储器件读取数据的方法中，基于字线电压生成读取数据。 读取数据包括从包括在非易失性存储器件中的多个扇区读取的数据。 基于读取数据和坏扇区信息传输数据不良扇区数据。 坏扇区数据对应于从包括在多个扇区中的至少一个坏扇区读取的数据。 通过检查坏扇区数据的错误位来更新坏扇区信息。 基于更新的坏扇区信息生成字线电压。