公开(公告)号：US08102688B2

公开(公告)日：2012-01-24

申请号：US12367213

申请日：2009-02-06

Applicant: Hoe-ju Chung ,  Jung-bae Lee

Inventor： Hoe-ju Chung ,  Jung-bae Lee

IPC: G11C5/02

CPC classification number: G11C5/063 ,  G11C5/02 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device includes a controller, a plurality of substrates, and a plurality of stacked memories that are spaced apart and sequence on each of the substrates. Each of the stacked memories includes an interface chip that is connected to the respective substrate and a plurality of memory chips that are stacked on the interface chip. The controller is configured to control the stacked memories. The interface chips are configured to forward a command signal from the controller through each interface chip in the sequence of stacked memories that is intervening between the controller and a selected stacked memory to which the command signal is directed. The interface chips may forward the command signal from one end of the sequence of the stacked memories on one of the substrates to the selected stacked memory, and forward a response signal from the selected stacked memory through the remaining stacked memories in the sequence on the substrate back to the controller or through the same sequence of stacked memories that was taken by the command signal.

Abstract translation: 半导体存储器件包括控制器，多个衬底以及在每个衬底上间隔开并且顺序的多个堆叠存储器。 每个堆叠的存储器包括连接到相应基板的接口芯片和堆叠在接口芯片上的多个存储器芯片。 控制器被配置为控制堆叠的存储器。 接口芯片被配置为通过介于控制器和命令信号所指向的所选择的堆叠存储器之间的堆叠存储器的顺序中的每个接口芯片从控制器转发命令信号。 接口芯片可以将命令信号从其中一个衬底上的堆叠存储器的序列的一端转发到所选择的堆叠存储器，并且将来自所选择的堆叠存储器的响应信号通过剩余的堆叠存储器按顺序在衬底上转发 返回到控制器或通过命令信号拍摄的相同的堆叠存储器序列。

公开(公告)号：US20120005555A1

公开(公告)日：2012-01-05

申请号：US13228763

申请日：2011-09-09

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: G06F11/08

CPC classification number: G06F11/1008

Abstract: A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

Abstract translation: 公开了一种包括存储器控制器和存储器以及相关方法的存储器系统。 该方法包括将与命令相关联的命令和错误检测/校正（EDC）数据从存储器控制器传送到存储器，解码该命令并并行执行与EDC数据相关的EDC操作，并且如果命令是写入 命令，延迟执行由写入命令指示的写入操作，直到完成EDC操作，否则立即执行由命令指示的操作，而不考虑完成EDC操作。

公开(公告)号：US08045405B2

公开(公告)日：2011-10-25

申请号：US11779349

申请日：2007-07-18

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: G11C29/00 ,  G11C7/00

CPC classification number: G06F11/1008 ,  G06F11/1076

Abstract: A memory system, memory, and memory system command protocol are disclosed. Within the memory system, a memory controller communicates a command to the memory, the command being selected from a set of commands including a write command and a plurality of non-write commands. A Hamming distance value calculated between a digital value indicating the write command and a digital value indicating any one of the plurality of non-write commands is greater than 1.

Abstract translation: 公开了一种存储器系统，存储器和存储器系统命令协议。 在存储器系统内，存储器控制器向存储器传送命令，该命令从包括写入命令和多个非写入命令的一组命令中选择。 在指示写入命令的数字值和指示多个非写入命令中的任何一个的数字值之间计算的汉明距离值大于1。

公开(公告)号：US08037390B2

公开(公告)日：2011-10-11

申请号：US11862409

申请日：2007-09-27

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: H03M13/00

CPC classification number: G06F11/1008

Abstract: A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

Abstract translation: 公开了一种包括存储器控制器和存储器以及相关方法的存储器系统。 该方法包括将与命令相关联的命令和错误检测/校正（EDC）数据从存储器控制器传送到存储器，解码该命令并并行执行与EDC数据相关的EDC操作，并且如果命令是写入 命令，延迟执行由写入命令指示的写入操作，直到完成EDC操作，否则立即执行由命令指示的操作，而不考虑完成EDC操作。

公开(公告)号：US08020068B2

公开(公告)日：2011-09-13

申请号：US11779345

申请日：2007-07-18

Applicant: Jung-Bae Lee

Inventor： Jung-Bae Lee

IPC: H03M13/00

CPC classification number: G06F11/1008

Abstract: A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

公开(公告)号：US20110199836A1

公开(公告)日：2011-08-18

申请号：US12958726

申请日：2010-12-02

Applicant: Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

Inventor： Cheol Kim ,  Sang-Kyun Park ,  Jung-Bae Lee ,  Jun-Phyo Lee

IPC: G11C29/12 ,  G11C7/10

CPC classification number: G11C11/4091 ,  G11C29/025 ,  G11C29/12005 ,  G11C29/1201 ,  G11C2029/1204

Abstract: The bit-line sense amplifier includes a driving-voltage control circuit and an amplifier. The driving-voltage control circuit generates a first test driving voltage having a voltage level of a pre-charge voltage, a second test driving voltage having a voltage level of a pre-charge voltage added by a voltage difference between a bit-line and a complementary bit-line, and a third test driving voltage having a voltage level of a pre-charge voltage subtracted by the voltage difference in a test mode. The amplifier senses and amplifies a voltage difference between the bit-line and the complementary bit-line.

Abstract translation: 位线读出放大器包括驱动电压控制电路和放大器。 驱动电压控制电路产生具有预充电电压的电压电平的第一测试驱动电压，具有由位线和位线之间的电压差相加的预充电电压的电压电平的第二测试驱动电压 以及第三测试驱动电压，其具有在测试模式下被电压差减去的预充电电压的电压电平。 放大器感测并放大位线和互补位线之间的电压差。

公开(公告)号：US20110072205A1

公开(公告)日：2011-03-24

申请号：US12885728

申请日：2010-09-20

Applicant: Dong-Hyuk LEE ,  Jung-Bae LEE ,  Ki-Won PARK

Inventor： Dong-Hyuk LEE ,  Jung-Bae LEE ,  Ki-Won PARK

IPC: G06F12/06

CPC classification number: G11C29/08 ,  G11C11/401

Abstract: A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell.

Abstract translation: 存储器装置包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储单元和控制设置电路。 控制设置电路基于每个存储器块是否包括至少一个不合标准的存储器单元，将存储器块分成至少第一组和第二组，并且分别设置第一组和第二组的控制参数。 基于存储器单元相对于至少一个控制参数的测试结果来识别不合格存储器单元。 第一组中的每个存储器块包括至少一个不合标准存储器单元，并且第二组中的每个存储器块都不包括不合格存储器单元。

公开(公告)号：US07855925B2

公开(公告)日：2010-12-21

申请号：US12071745

申请日：2008-02-26

Applicant: Uk-song Kang ,  Jung-bae Lee

Inventor： Uk-song Kang ,  Jung-bae Lee

IPC: G11C7/10

CPC classification number: G11C5/025 ,  G11C5/04

Abstract: A multi memory chip stacked on a multi core CPU includes a plurality of memories, each memory corresponding to a CPU core from among the CPU cores and being configured to directly transmit data between the other memories of the multi memory chip.

Abstract translation: 堆叠在多核CPU上的多存储器芯片包括多个存储器，每个存储器对应于CPU核心中的CPU核心，并且被配置为直接在多存储器芯片的其他存储器之间传输数据。

公开(公告)号：US20100191880A1

公开(公告)日：2010-07-29

申请号：US12750906

申请日：2010-03-31

Applicant: Jung-bae LEE

Inventor： Jung-bae LEE

IPC: G06F13/00 ,  H03K17/16 ,  H03K19/003

CPC classification number: G11C5/00 ,  G11C5/06 ,  G11C7/1048 ,  G11C11/409 ,  H05K1/0246

Abstract: A memory module and a related memory system are disclosed. The memory module comprises a semiconductor memory having a data output buffer, a data input buffer, a command/address input buffer and a first termination resistor unit connected to a data bus. The memory module further comprises a second termination resistor unit connected to an internal command/address bus. First and second termination resistor units are preferably of different resistive value and/or type.

Abstract translation: 公开了一种存储器模块和相关存储器系统。 存储器模块包括具有数据输出缓冲器，数据输入缓冲器，连接到数据总线的命令/地址输入缓冲器和第一终端电阻器单元的半导体存储器。 存储器模块还包括连接到内部命令/地址总线的第二终端电阻器单元。 第一和第二终端电阻器单元优选地具有不同的电阻值和/或类型。

公开(公告)号：US20090303802A1

公开(公告)日：2009-12-10

申请号：US12539840

申请日：2009-08-12

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G11C7/10 ,  G11C5/14 ,  G11C7/00 ,  H03K19/003

CPC classification number: G11C5/04 ,  G11C5/06 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/409

Abstract: A semiconductor memory module includes a memory module board having at least one semiconductor memory device. The semiconductor memory device includes a data input buffer that receives data and a first reference voltage via first and second input terminals, a command/address buffer that receives a command/address signal and a second reference voltage via first and second input terminals, and a first termination resistor unit connected to the first input terminal of the data input buffer. The semiconductor memory module further includes a second termination resistor unit located on the memory module board and connected to an internal command/address bus. The first termination resistor unit includes a first resistor connected between a first voltage source and the first input terminal of the data input buffer, and the second termination resistor unit includes a second resistor connected between a second voltage source and the first input terminal of the command/address input buffer.

Abstract translation: 半导体存储器模块包括具有至少一个半导体存储器件的存储器模块板。 半导体存储器件包括经由第一和第二输入端子接收数据和第一参考电压的数据输入缓冲器，经由第一和第二输入端子接收命令/地址信号和第二参考电压的命令/地址缓冲器，以及 连接到数据输入缓冲器的第一输入端的第一终端电阻单元。 半导体存储器模块还包括位于存储器模块板上并连接到内部命令/地址总线的第二终端电阻器单元。 第一终端电阻器单元包括连接在第一电压源和数据输入缓冲器的第一输入端之间的第一电阻器，第二终端电阻器单元包括连接在第二电压源和命令的第一输入端之间的第二电阻器 /地址输入缓冲区。