公开(公告)号：US20080256414A1

公开(公告)日：2008-10-16

申请号：US12044183

申请日：2008-03-07

Applicant: Hoe-Ju CHUNG ,  Jung-Bae LEE

Inventor： Hoe-Ju CHUNG ,  Jung-Bae LEE

IPC: G06F11/10 ,  G11C5/06

CPC classification number: G06F11/1008 ,  G11C5/02 ,  G11C5/04 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1045 ,  G11C2029/0411 ,  H04L1/0041 ,  H04L1/0057

Abstract: A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane.

Abstract translation: 系统，设备和相关方法用于经由包括所选择的数据通道的多个数据通道来传送数据。 在第一操作模式中，经由包括所选择的数据通道的多个数据通道来传送有效载荷数据和相关的补充数据。 在第二种操作模式中，只有有效载荷数据经由多个数据通道被传送，除了所选择的数据通道。

公开(公告)号：US20110314349A1

公开(公告)日：2011-12-22

申请号：US13221418

申请日：2011-08-30

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: H04L1/18

CPC classification number: H04L1/1671 ,  H04L1/0025 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/0288 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03885

Abstract: A system having a transmission unit transmitting an output data signal formed from output data and related error detection code and a corresponding receiving unit. The output data signal is pre-emphasized by a pre-emphasis driver in the transmission unit. The receiving unit includes an equalizer equalizing the received output data signal and an error detector analyzing the error detection code to determine whether a bit error is present in the received data. Upon successive data transmission failures either an equalization coefficient in the equalizer or a pre-emphasis coefficient in the pre-emphasis driver are changed.

Abstract translation: 一种具有发送单元的系统，该发送单元发送由输出数据和相关错误检测码形成的输出数据信号和相应的接收单元。 输出数据信号由传输单元中的预加重驱动器预先强调。 接收单元包括均衡接收的输出数据信号的均衡器和分析错误检测码的误差检测器，以确定接收数据中是否存在位错误。 在连续数据传输故障时，均衡器中的均衡系数或预加重驱动器中的预加重系数被改变。

公开(公告)号：US20080013397A1

公开(公告)日：2008-01-17

申请号：US11863141

申请日：2007-09-27

Applicant: Chul-Woo PARK ,  Sung-Hoon KIM ,  Hyuk-Joon KWON ,  Jung-Bae LEE ,  Youn-Sik PARK

Inventor： Chul-Woo PARK ,  Sung-Hoon KIM ,  Hyuk-Joon KWON ,  Jung-Bae LEE ,  Youn-Sik PARK

IPC: G11C8/08

CPC classification number: H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

公开(公告)号：US20080184002A1

公开(公告)日：2008-07-31

申请号：US11779349

申请日：2007-07-18

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: G06F12/00 ,  G06F11/16

CPC classification number: G06F11/1008 ,  G06F11/1076

Abstract: A memory system, memory, and memory system command protocol are disclosed. Within the memory system, a memory controller communicates a command to the memory, the command being selected from a set of commands including a write command and a plurality of non-write commands. A Hamming distance value calculated between a digital value indicating the write command and a digital value indicating any one of the plurality of non-write commands is greater than 1.

Abstract translation: 公开了一种存储器系统，存储器和存储器系统命令协议。 在存储器系统内，存储器控制器向存储器传送命令，该命令从包括写入命令和多个非写入命令的一组命令中选择。 在指示写入命令的数字值和指示多个非写入命令中的任何一个的数字值之间计算的汉明距离值大于1。

公开(公告)号：US20080181030A1

公开(公告)日：2008-07-31

申请号：US11862412

申请日：2007-09-27

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: G11C7/00

CPC classification number: G06F11/1008 ,  G06F11/1076

Abstract: A memory system, memory, and memory system command protocol are disclosed. Within the memory system, a memory controller communicates a command to the memory, the command being selected from a set of commands including a write command and a plurality of non-write commands. A Hamming distance value calculated between a digital value indicating the write command and a digital value indicating any one of the plurality of non-write commands is greater than 1.

公开(公告)号：US20080102830A1

公开(公告)日：2008-05-01

申请号：US11873854

申请日：2007-10-17

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: H04Q7/32

CPC classification number: H04W48/16 ,  H04W8/183

Abstract: A method and an apparatus for connecting a network in a portable terminal. The method for connecting a network in a portable terminal includes searching a network from which a signal is received, receiving network identifying information from the searched network, retrieving connection information corresponding to the network identifying information, from network connection information stored in the portable terminal in advance, and setting the retrieved network connection information as the network connection information of the portable terminal.

Abstract translation: 一种用于连接便携式终端中的网络的方法和装置。 用于连接便携式终端中的网络的方法包括从存储在便携式终端中的网络连接信息中搜索从哪个接收到信号的网络，从所搜索的网络接收网络识别信息，检索与网络识别信息相对应的连接信息 提前，并将所检索的网络连接信息设置为便携式终端的网络连接信息。

公开(公告)号：US20120005555A1

公开(公告)日：2012-01-05

申请号：US13228763

申请日：2011-09-09

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: G06F11/08

CPC classification number: G06F11/1008

Abstract: A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

Abstract translation: 公开了一种包括存储器控制器和存储器以及相关方法的存储器系统。 该方法包括将与命令相关联的命令和错误检测/校正（EDC）数据从存储器控制器传送到存储器，解码该命令并并行执行与EDC数据相关的EDC操作，并且如果命令是写入 命令，延迟执行由写入命令指示的写入操作，直到完成EDC操作，否则立即执行由命令指示的操作，而不考虑完成EDC操作。

公开(公告)号：US20110072205A1

公开(公告)日：2011-03-24

申请号：US12885728

申请日：2010-09-20

Applicant: Dong-Hyuk LEE ,  Jung-Bae LEE ,  Ki-Won PARK

Inventor： Dong-Hyuk LEE ,  Jung-Bae LEE ,  Ki-Won PARK

IPC: G06F12/06

CPC classification number: G11C29/08 ,  G11C11/401

Abstract: A memory device comprises a memory cell array comprising a plurality of memory blocks each comprising a plurality of memory cells and a control setting circuit. The control setting circuit divides the memory blocks into at least first and second groups based on whether each of the memory blocks comprises at least one substandard memory cell, and sets individually control parameters of the first and second groups. The substandard memory cells are identified based on test results of the memory cells with respect to at least one of the control parameters. Each memory block in the first group comprises at least one substandard memory cell, and each memory block in the second group comprises no substandard memory cell.

Abstract translation: 存储器装置包括存储单元阵列，其包括多个存储块，每个存储块包括多个存储单元和控制设置电路。 控制设置电路基于每个存储器块是否包括至少一个不合标准的存储器单元，将存储器块分成至少第一组和第二组，并且分别设置第一组和第二组的控制参数。 基于存储器单元相对于至少一个控制参数的测试结果来识别不合格存储器单元。 第一组中的每个存储器块包括至少一个不合标准存储器单元，并且第二组中的每个存储器块都不包括不合格存储器单元。

公开(公告)号：US20090147559A1

公开(公告)日：2009-06-11

申请号：US12326940

申请日：2008-12-03

Applicant: Yun-Sang LEE ,  Woo-Jung SUN ,  Jung-Bae LEE

Inventor： Yun-Sang LEE ,  Woo-Jung SUN ,  Jung-Bae LEE

IPC: G11C11/4091 ,  G11C7/06

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4094

Abstract: A memory cell array with open bit line structure includes a first sub memory cell array, a second sub memory cell array, a sense-amplifier/precharge circuit, first capacitors and second capacitors. The first sub memory cell array is activated in response to a first word line enable signal, and the second sub memory cell array is activated in response to a second word line enable signal. The sense-amplifier/precharge circuit is connected to the first sub memory cell array through first bit lines and to the second sub memory cell array through second bit lines, and the sense-amplifier/precharge circuit precharges the first bit lines and the second bit lines and amplifies data provided from the first sub memory cell array and the second sub memory cell array.

Abstract translation: 具有开放位线结构的存储单元阵列包括第一子存储单元阵列，第二子存储单元阵列，读出放大器/预充电电路，第一电容器和第二电容器。 第一子存储单元阵列响应于第一字线使能信号被激活，并且第二子存储单元阵列响应于第二字线使能信号被激活。 感测放大器/预充电电路通过第一位线连接到第一子存储单元阵列，并通过第二位线连接到第二子存储单元阵列，并且读出放大器/预充电电路对第一位线和第二位进行预充电 并且放大从第一子存储单元阵列和第二子存储单元阵列提供的数据。

公开(公告)号：US20080208537A1

公开(公告)日：2008-08-28

申请号：US12037324

申请日：2008-02-26

Applicant: Jung-Bae LEE ,  Ki-Chul CHUN

Inventor： Jung-Bae LEE ,  Ki-Chul CHUN

IPC: G06F15/00

CPC classification number: G11C29/50 ,  G11C29/50012 ,  G11C2029/1206

Abstract: A circuit measuring the operating speed of a semiconductor memory chip in relation to a defined asynchronous access time is disclosed. The circuit includes a test signal path extending between a test input pad and a test output pad and is formed by a plurality of test signal path segments and at least one delay element associated with at least one of the plurality of test signal path segments, such that a delay time for a test signal communicated through the test signal path is indicative of the actual asynchronous access time for the semiconductor memory chip. Each one of the plurality of test signal path segments is either an interior test signal path segment or an exterior test signal path segment.

Abstract translation: 公开了相对于定义的异步访问时间测量半导体存储器芯片的操作速度的电路。 电路包括在测试输入焊盘和测试输出焊盘之间延伸的测试信号路径，并且由多个测试信号路径段和与多个测试信号路径段中的至少一个相关联的至少一个延迟元件形成， 通过测试信号路径传送的测试信号的延迟时间表示半导体存储器芯片的实际异步访问时间。 多个测试信号路径段中的每一个是内部测试信号路径段或外部测试信号路径段。