公开(公告)号：US10659030B1

公开(公告)日：2020-05-19

申请号：US15874860

申请日：2018-01-18

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Benjamin J. Cahill

IPC: H03K17/00 ,  G06F13/40 ,  G06F9/46

Abstract: A transactional memory (TM) of an island-based network flow processor (IB-NFP) integrated circuit receives a Stats Add-and-Update (AU) command across a command mesh of a Command/Push/Pull (CPP) data bus from a processor. A memory unit of the TM stores a plurality of first values in a corresponding set of memory locations. A hardware engine of the TM receives the AU, performs a pull across other meshes of the CPP bus thereby obtaining a set of addresses, uses the pulled addresses to read the first values out of the memory unit, adds the same second value to each of the first values thereby generating a corresponding set of updated first values, and causes the set of updated first values to be written back into the plurality of memory locations. Even though multiple count values are updated, there is only one bus transaction value sent across the CPP bus command mesh.

公开(公告)号：US10474465B2

公开(公告)日：2019-11-12

申请号：US14267362

申请日：2014-05-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  G06F9/38

Abstract: A pipelined run-to-completion processor executes a pop stack absolute instruction. The instruction includes an opcode, an absolute pointer value, a flag don't touch bit, and predicate bits. If a condition indicated by the predicate bits is not true, then the opcode operation is not performed. If the condition is true, then the stack of the processor is popped thereby generating an operand A. The absolute pointer value is used to identify a particular register of the stack, and the content of that particular register is an operand B. The arithmetic logic operation specified by the opcode is performed using operand A and operand B thereby generating a result, and the content of the particular register is replaced with the result. If the flag don't touch bit is set to a particular value, then the flag bits (carry flag and zero flag) are not affected by the instruction execution.

公开(公告)号：US10419348B2

公开(公告)日：2019-09-17

申请号：US15924193

申请日：2018-03-17

Applicant: Netronome Systems, Inc.

Inventor： Roelof Nico du Toit ,  Jacques Fourie ,  Peter Liudmilov Djalaliev

IPC: H04L12/801 ,  H04L29/06

Abstract: A TCP connection is established between a client and a server, such that packets communicated across the TCP connection pass through a proxy. Based at least in part on a result of monitoring packets flowing across the TCP connection, the proxy determines whether to split the TCP control loop into two TCP control loops so that packets can be inspected more thoroughly. If the TCP control loop is split, then a first TCP control loop manages flow between the client the proxy and a second TCP control loop manages flow between the proxy and the server. Due to the two control loops, packets can be held on the proxy long enough to be analyzed. In some circumstances, a decision is then made to stop inspecting. The two TCP control loops are merged into a single TCP control loop, and thereafter the proxy passes packets of the TCP connection through unmodified.

公开(公告)号：US10365681B1

公开(公告)日：2019-07-30

申请号：US15256588

申请日：2016-09-04

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F1/00 ,  G06F1/06

Abstract: A multiprocessor system includes several processors, a prefetching instruction code interface block, a prefetching data code interface block, a Shared Local Memory (SLMEM), and Clock Gapping Circuits (CGCs). Each processor has the same address map. Each fetches instructions from SLMEM via the instruction interface block. Each accesses data from/to SLMEM via the data interface block. The interface blocks and the SLMEM are clocked at a faster rate than the processors. The interface blocks have wide prefetch lines of the width of the SLMEM. The data interface block supports no-wait single-byte data writes from the processors, and also supports no-wait multi-byte data writes. An address translator prevents one processor from overwriting the stack of another. If a requested instruction or data is not available in the appropriate prefetching circuit, then the clock signal of the requesting processor is gapped until the instruction or data can be returned to the requesting processor.

公开(公告)号：US10362093B2

公开(公告)日：2019-07-23

申请号：US14151699

申请日：2014-01-09

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: H04L29/06 ,  H04L29/08

Abstract: Multiple processors share access, via a bus, to a pipelined NFA engine. The NFA engine can implement an NFA of the type that is not a DFA (namely, it can be in multiple states at the same time). One of the processors communicates a configuration command, a go command, and an event generate command across the bus to the NFA engine. The event generate command includes a reference value. The configuration command causes the NFA engine to be configured. The go command causes the configured NFA engine to perform a particular NFA operation. Upon completion of the NFA operation, the event generate command causes the reference value to be returned back across the bus to the processor.

公开(公告)号：US10250528B2

公开(公告)日：2019-04-02

申请号：US14264003

申请日：2014-04-28

Applicant: Netronome Systems, Inc.

Inventor： Nicolaas J. Viljoen ,  Sandra Scott-Hayward

IPC: G06F15/173 ,  H04L12/931 ,  H04L12/751 ,  H04L12/715 ,  H04L12/723 ,  H04L12/773 ,  H04L12/24 ,  H04L12/26

Abstract: A first switch in a MPLS network receives a plurality of packets that are part of a pair of flows. The first switch performs a packet prediction learning algorithm on the first plurality of packets and generates packet prediction information that is communicated to a second switch within the MPLS network utilizing an Operations, Administration, and Maintenance (OAM) packet (message). In a first example, the first switch communicates a packet prediction information notification to a Network Operations Center (NOC) that in response communicates a packet prediction control signal to the second switch. In a second example, the first switch does not communicate a packet prediction information notification. In the first example, the second switch utilizes the packet prediction control signal to determine if the packet prediction information is to be utilized. In the second example, second switch independently determines if the packet prediction information is to be used.

公开(公告)号：US10191867B1

公开(公告)日：2019-01-29

申请号：US15256583

申请日：2016-09-04

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F13/14 ,  G06F13/16 ,  G06F9/4401 ,  G06F9/44

Abstract: A multiprocessor system includes several processors, a Shared Local Memory (SLMEM), and an interface circuit for interfacing the system to an external posted transaction bus. Each processor has the same address map. Each fetches instructions from SLMEM, and accesses data from/to SLMEM. A processor can initiate a read transaction on the posted transaction bus by doing an AHB-S bus write to a particular address. The AHB-S write determines the type of transaction initiated and also specifies an address in a shared memory in the interface circuit. The interface circuit uses information from the AHB-S write to generate a command of the correct format. The interface circuit outputs the command onto the posted transaction bus, and then receives read data back from the posted transaction bus, and then puts the read data into the shared memory at the address specified by the processor in the original AHB-S bus write.

公开(公告)号：US10044619B1

公开(公告)日：2018-08-07

申请号：US14587513

申请日：2014-12-31

Applicant: Netronome Systems, Inc.

Inventor： Johann Heinrich Tönsing ,  Roelof Nico DuToit ,  Gysbert Floris van Beek Van Leeuwen ,  Jan Neil Viljoen ,  David Wells ,  Leon Johannes Brits ,  Jan Christoffel DuToit

IPC: H04L12/28 ,  H04L12/56 ,  H04L12/801 ,  H04L12/891 ,  H04L12/851 ,  H04L12/813

Abstract: A system and method for handling a digital electronic flow between a first and second entity in which a flow policy is determined that is to be applied to the flow and the flow is then directed along a path in accordance with the policy. An ID is supplied for each flow and a tag associated with each flow which indicates the policy to be applied to its associated flow. Flows are also associated with one another, with associated flows having associated policies. In particular the flow may be processed or forwarded. The path may include a graph structure and virtual applications.

公开(公告)号：US10009270B1

公开(公告)日：2018-06-26

申请号：US14634844

申请日：2015-03-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/741 ,  H04L12/947

CPC classification number: H04L45/745 ,  H04L45/54 ,  H04L49/25

Abstract: A Software-Defined Networking (SDN) switch includes external network ports for receiving external network traffic onto the SDN switch, external network ports for transmitting external network traffic out of the SDN switch, a first Network Flow Switch (NFX) integrated circuit that has multiple network ports and that maintains a first flow table, another Network Flow Switch (NFX) integrated circuit that has multiple network ports and that maintains a second flow table, a Network Flow Processor (NFP) circuit that maintains a third flow table, and a controller processor circuit that maintains a fourth flow table. The controller processor circuit is coupled by a serial bus to the NFP circuit but is not directly coupled by any network port to either the NFP circuit nor the first NFX integrated circuit nor the second NFX integrated circuit.

公开(公告)号：US09998374B1

公开(公告)日：2018-06-12

申请号：US14634845

申请日：2015-03-01

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Stuart C. Wray

IPC: H04L12/741 ,  H04L12/947 ,  H04L12/931

CPC classification number: H04L45/745 ,  H04L45/54 ,  H04L49/25 ,  H04L49/35

Abstract: A method involves a Software-Defined Networking (SDN) switch that includes multiple Network Flow Switch (NFX) integrated circuits, a Network Flow Processor (NFP) circuit, and a controller processor. The controller processor is coupled to the NFP circuit by a serial bus. A flow table is maintained on each of the NFX integrated circuits. A SDN flow table is maintained on the NFP circuit. A copy of each of the flow tables is maintained on the NFP circuit. Another SDN flow table is maintained on the controller processor. A SDN protocol stack is executed on the controller processor. A SDN protocol message is received onto the SDN switch via one of the NFX integrated circuits. The SDN protocol message is communicated across a network link to the NFP circuit, and across the serial bus from the NFP circuit to the controller processor such that the SDN protocol message is received and processed by the SDN protocol stack executing on the controller processor.