公开(公告)号：US09899978B2

公开(公告)日：2018-02-20

申请号：US15466661

申请日：2017-03-22

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso ,  Toru Ido

IPC: H03F3/217 ,  H03G3/30 ,  H03F1/34 ,  H03G7/00

CPC classification number: H03G3/3089 ,  H03F1/26 ,  H03F1/32 ,  H03F1/34 ,  H03F3/187 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/2173 ,  H03F3/2175 ,  H03F2200/102 ,  H03F2200/339 ,  H03F2200/432 ,  H03G7/002 ,  H03G7/007

Abstract: This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).

公开(公告)号：US20160329867A1

公开(公告)日：2016-11-10

申请号：US14707846

申请日：2015-05-08

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso ,  Emmanuel Philippe Christian Hardy

IPC: H03F1/32 ,  H03F3/183

CPC classification number: H03F1/3241 ,  H03F1/3258 ,  H03F1/3264 ,  H03F3/183 ,  H03F2200/03 ,  H03F2201/3233 ,  H04R3/08 ,  H04R5/04 ,  H04R29/003 ,  H04R2420/03 ,  H04R2460/03

Abstract: This application relates to audio amplifier circuitry (100). An amplifier module (103) is located in a signal path between an input (101) and an output (102). A detection module (106) is configured to detect a characteristic of a load (104) electrically coupled, in use, to the output. A distortion setting controller (107) is provided for selecting one of a plurality of stored distortion settings {pi} based on the detected characteristic of the load; and a pre-distortion module (105) is configured to apply a first transfer function to a signal in the signal path prior to said amplifier module. The first transfer function is based on the selected distortion setting and for at least one of the stored distortion settings the corresponding first transfer function comprises a non-linear distortion function.

Abstract translation: 本申请涉及音频放大器电路（100）。 放大器模块（103）位于输入（101）和输出（102）之间的信号路径中。 检测模块（106）被配置为检测在使用中电耦合到输出的负载（104）的特性。 提供失真设定控制器（107），用于根据检测到的负载特性来选择多个存储的失真设置{pi}中的一个; 并且预失真模块（105）被配置为在所述放大器模块之前对信号路径中的信号应用第一传递函数。 第一传递函数基于所选择的失真设置，并且对于存储的失真设置中的至少一个，对应的第一传递函数包括非线性失真函数。

公开(公告)号：US20160149581A1

公开(公告)日：2016-05-26

申请号：US15009405

申请日：2016-01-28

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso

IPC: H03L7/099 ,  H03G5/00 ,  G06F3/16

CPC classification number: H03L7/099 ,  G06F3/162 ,  H03G5/00 ,  H03G5/005 ,  H03L7/08 ,  H03L7/087 ,  H03L7/14 ,  H03L7/18 ,  H03L2207/50

Abstract: A clock generator receives first and second clock signals, and input representing a desired frequency ratio. A comparison is made between frequencies of an output clock signal and the first clock signal, and a first error signal represents the difference between the desired frequency ratio and this comparison result. The first error signal is filtered. A comparison is made between frequencies of the output clock signal and the second clock signal, and a second error signal represents the difference between the filtered first error signal and this comparison result. The second error signal is filtered. A numerically controlled oscillator receives the filtered second error signal and generates an output clock signal. As a result, the output clock signal has the jitter characteristics of the first input clock signal over a useful range of jitter frequencies and the frequency accuracy of the second input clock signal.

公开(公告)号：US20160065158A1

公开(公告)日：2016-03-03

申请号：US14836006

申请日：2015-08-26

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： John Paul Lesso ,  Toru Ido

IPC: H03G3/30 ,  H03F3/217 ,  H03F1/34

CPC classification number: H03G3/3089 ,  H03F1/26 ,  H03F1/32 ,  H03F1/34 ,  H03F3/187 ,  H03F3/217 ,  H03F3/2171 ,  H03F3/2173 ,  H03F3/2175 ,  H03F2200/102 ,  H03F2200/339 ,  H03F2200/432 ,  H03G7/002 ,  H03G7/007

Abstract: This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).

Abstract translation: 本申请涉及D类放大器电路（200）。 调制器（201）基于调制器输入信号（Dm）控制D类输出级（202），以产生代表输入信号（Din）的输出信号（Vout）。 可以包括ADC（207）的误差块（205）从输出信号和输入信号产生误差信号（＆egr）。 在各种实施例中，基于输入信号（Din）的振幅的指示，可以对误差信号（＆egr）贡献于调制器输入信号（Dm）的程度是可变的。 误差信号可以在信号选择器块（203）的第一输入（204）处被接收。 可以在信号选择器块（203）的第二输入（206）处接收输入信号。 信号选择器块可以在第一和第二操作模式下操作，其中在第一模式中，调制器输入信号至少部分地基于误差信号; 并且在第二模式中，调制器输入信号基于数字输入信号，并且与误差信号无关。 误差信号可以用于降低高信号电平的失真，但不会在低信号电平下使用，因此低信号电平的噪声基底不依赖于误差块的分量（205）。