公开(公告)号：US20220066898A1

公开(公告)日：2022-03-03

申请号：US17005114

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Todd A. Marquart ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Kishore K. Muchherla ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F11/30 ,  G06F11/14 ,  G06F11/07 ,  G06F11/32 ,  G06F1/30

Abstract: A system includes a processing device and a memory device coupled to the processing device. The memory device can include a cyclic buffer portion and a snapshot portion. The processing device can store time based telemetric sensor data in the cyclic buffer portion, copy an amount of the telemetric sensor data from the cyclic buffer portion to the snapshot portion in response to a trigger event, operate the cyclic buffer portion with a first trim tailored to a performance target of the cyclic buffer portion, and operate the snapshot portion with a second trim tailored to a performance target of the snapshot portion.

公开(公告)号：US20220028808A1

公开(公告)日：2022-01-27

申请号：US16940040

申请日：2020-07-27

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Akira Goda

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/48 ,  H01L21/48 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573

Abstract: An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.

公开(公告)号：US11201164B2

公开(公告)日：2021-12-14

申请号：US16546821

申请日：2019-08-21

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Yushi Hu

IPC: H01L21/28 ,  H01L27/11582

Abstract: Some embodiments include a NAND memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels, and is spaced from the control gate regions by charge-blocking material. The charge-trapping material along vertically adjacent wordline levels is spaced by intervening regions through which charge migration is impeded. Channel material extends vertically along the stack and is spaced from the charge-trapping material by charge-tunneling material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20210375893A1

公开(公告)日：2021-12-02

申请号：US17445134

申请日：2021-08-16

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Akira Goda ,  Sanh D. Tang ,  Gurtej S. Sandhu ,  Litao Yang ,  Haitao Liu

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L29/24 ,  H01L29/786 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/528

Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11127747B2

公开(公告)日：2021-09-21

申请号：US16549519

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Akira Goda ,  Sanh D. Tang ,  Gurtej S. Sandhu ,  Litao Yang ,  Haitao Liu

IPC: H01L27/11524 ,  H01L27/1157 ,  H01L29/24 ,  H01L29/786 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/528

Abstract: A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US20210257387A1

公开(公告)日：2021-08-19

申请号：US17308766

申请日：2021-05-05

Applicant: Micron Technology, Inc.

Inventor： Guangyu Huang ,  Haitao Liu ,  Chandra Mouli ,  Justin B. Dorhout ,  Sanh D. Tang ,  Akira Goda

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L49/02

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion. Some embodiments include methods of forming integrated structures.

公开(公告)号：US20210217768A1

公开(公告)日：2021-07-15

申请号：US16743422

申请日：2020-01-15

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Akira Goda

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L21/78 ,  H01L29/51

Abstract: Some embodiments include a method of forming a memory device. An assembly is formed to have channel structures extending through a stack of alternating insulative and conductive levels and into a first material under the stack. The assembly is inverted so that the first material is above the stack, and so that first regions of the channel structures are under the stack. At least some of the first regions are electrically coupled with control circuitry. At least some of the first material is removed, and second regions of the channel structures are exposed. Conductively-doped semiconductor material is formed adjacent the exposed second regions of the channel structures. Dopant is out-diffused from the conductively-doped semiconductor material into the channel structures. Some embodiments include memory devices (e.g., NAND memory assemblies).

公开(公告)号：US11056571B2

公开(公告)日：2021-07-06

申请号：US16444532

申请日：2019-06-18

Applicant: Micron Technology, Inc.

Inventor： Ankit Sharma ,  Akira Goda

IPC: H01L29/51 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66

Abstract: A memory cell comprises, in the following order, channel material, a charge-passage structure, programmable material, a charge-blocking region, and a control gate. The charge-passage structure comprises a first material closest to the channel material, a third material furthest from the channel material, and a second material between the first material and the third material. The first and third materials comprise SiO2. The second material has a thickness of 0.4 nanometer to 5.0 nanometers and comprises SiOx, where “x” is less than 2.0 and greater than 0. Other embodiments are disclosed.

公开(公告)号：US11018255B2

公开(公告)日：2021-05-25

申请号：US16110217

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Guangyu Huang ,  Chandra V. Mouli ,  Akira Goda ,  Deepak Chandra Pandey ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/423 ,  H01L29/267 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/02 ,  H01L21/44 ,  H01L27/11582 ,  H01L29/08 ,  H01L21/425 ,  H01L29/10 ,  H01L29/786 ,  H01L27/1157 ,  H01L29/36 ,  H01L29/49 ,  H01L29/417

Abstract: A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.

公开(公告)号：US20210134825A1

公开(公告)日：2021-05-06

申请号：US17145131

申请日：2021-01-08

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/11573 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C16/08 ,  H01L23/532 ,  H01L21/28

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.