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    DYNAMIC STEP VOLTAGE LEVEL ADJUSTMENT
    1.
    发明申请
    DYNAMIC STEP VOLTAGE LEVEL ADJUSTMENT 有权

    公开(公告)号：US20250095746A1

    公开(公告)日：2025-03-20

    申请号：US18967011

    申请日：2024-12-03

    Applicant: Micron Technology, Inc.

    Inventor： Carmine Miccoli ,  Andrew Bicksler

    IPC: G11C16/12 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32

    Abstract: Processing logic in a memory device receives a request to execute a programming operation on a set of memory cells of the memory device. A first set of programming pulses corresponding to a first step voltage level are caused to be applied to program the set of memory cells. The processing logic determines that a programming voltage level associated with a programming pulse of the first set of one or more programming pulses satisfies a condition. The first set voltage is adjusted to a second step voltage level in response to the condition being satisfied.

    Dynamic step voltage level adjustment
    3.
    发明授权
    Dynamic step voltage level adjustment 有权

    公开(公告)号：US12190957B2

    公开(公告)日：2025-01-07

    申请号：US17939273

    申请日：2022-09-07

    Applicant: Micron Technology, Inc.

    Inventor： Carmine Miccoli ,  Andrew Bicksler

    IPC: G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/32

    Abstract: Processing logic in a memory device receives a request to execute a programming operation on a set of memory cells of the memory device. A first set of programming pulses corresponding to a first step voltage level are caused to be applied to one or more wordlines associated with the set of memory cells. The processing logic determines that a programming voltage level associated with a programming pulse of the first set of programming pulses satisfies a condition. A second set of programming pulses corresponding to a second step voltage level is caused to be applied to the one or more wordlines associated with the set of memory cells in response to the condition being satisfied.

    SEPARATE PARTITION FOR BUFFER AND SNAPSHOT MEMORY
    5.
    发明申请
    SEPARATE PARTITION FOR BUFFER AND SNAPSHOT MEMORY 有权

    公开(公告)号：US20220350517A1

    公开(公告)日：2022-11-03

    申请号：US17846462

    申请日：2022-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

    IPC: G06F3/06

    Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

    Techniques for suspend operations
    7.
    发明授权
    Techniques for suspend operations 有权

    公开(公告)号：US12189522B2

    公开(公告)日：2025-01-07

    申请号：US17853219

    申请日：2022-06-29

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Justin Bates ,  Ryan Hrinya ,  Fulvio Rori ,  Chiara Cerafogli ,  Carmine Miccoli

    IPC: G06F12/02

    Abstract: Methods, systems, and devices for suspend operations are described. A memory device may perform a write operation including one or more programming phases and one or more verify phases. The memory device may receive a read command while performing the write operation and determine whether the verify phase of the write operation is complete. The memory device may suspend a performance of the write operation in response to determining that the verify phase of the write operation is complete. The memory device may transmit first information for the write operation from a first latch to a volatile memory device in response to suspending the performance of the write operation. The memory device may perform a read operation associated with the read command in response to suspending the performance of the write operation and transferring the first information.

    DYNAMIC STEP VOLTAGE LEVEL ADJUSTMENT
    8.
    发明申请
    DYNAMIC STEP VOLTAGE LEVEL ADJUSTMENT 有权

    公开(公告)号：US20230133227A1

    公开(公告)日：2023-05-04

    申请号：US17939273

    申请日：2022-09-07

    Applicant: Micron Technology, Inc.

    Inventor： Carmine Miccoli ,  Andrew Bicksler

    IPC: G11C16/12 ,  G11C16/10 ,  G11C16/08

    Abstract: Processing logic in a memory device receives a request to execute a programming operation on a set of memory cells of the memory device. A first set of programming pulses corresponding to a first step voltage level are caused to be applied to one or more wordlines associated with the set of memory cells. The processing logic determines that a programming voltage level associated with a programming pulse of the first set of programming pulses satisfies a condition. A second set of programming pulses corresponding to a second step voltage level is caused to be applied to the one or more wordlines associated with the set of memory cells in response to the condition being satisfied.

    Separate partition for buffer and snapshot memory
    9.
    发明授权
    Separate partition for buffer and snapshot memory 有权

    公开(公告)号：US11385819B2

    公开(公告)日：2022-07-12

    申请号：US16995682

    申请日：2020-08-17

    Applicant: Micron Technology, Inc.

    Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

    IPC: G06F3/06

    Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

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