公开(公告)号：US5177597A

公开(公告)日：1993-01-05

申请号：US623026

申请日：1990-12-06

申请人： Yoshihiko Ogawa ,  Seijiro Yasuki ,  Kiyoyuki Kawai

发明人： Yoshihiko Ogawa ,  Seijiro Yasuki ,  Kiyoyuki Kawai

IPC分类号： H04N7/015 ,  H04N7/08 ,  H04N7/081 ,  H04N11/24

CPC分类号： H04N7/015 ,  H04N11/006 ,  H04N19/60 ,  H04N19/30

摘要： A television signal multiplexing and demultiplexing system includes a signal separation circuit for separating from a composite color television signal a plurality of first television signals serving as additional information for making the quality of a television picture higher and a second television signal. A matrix operation circuit performs a vertical matrix operation on the first television signals so as to dispose each of the first television signals in a different vertical band, thereby producing operation outputs. A delay circuit delays the operation outputs by different amounts of delay to produce delayed outputs. A multiplexing circuit multiplexes the delayed outputs on different horizontal scanning lines of the second television signal to produce a multiplexed output. A demultiplexing circuit demultiplexes the multiplexed output into the operation outputs and the second television signal. A recovering circuit recovers the first television signals by performing a matrix operation which is the inverse of the matrix operation on the separated operation outputs to recover the first television signal.

公开(公告)号：US5153845A

公开(公告)日：1992-10-06

申请号：US612973

申请日：1990-11-15

申请人： Yoshihiko Ogawa ,  Seijiro Yasuki ,  Kiyoyuki Kawai

发明人： Yoshihiko Ogawa ,  Seijiro Yasuki ,  Kiyoyuki Kawai

IPC分类号： H03H17/00 ,  H03H17/06

CPC分类号： H03H17/0685

摘要： A time base conversion circuit including a data interpolating circuit for converting a digital signal of sampling frequency fs into a digital signal having M (M is a positive integer) samples per N/fs (N is another positive integer) cycle without loosing data during the interpolating process, a register for holding M data which are output from the data interpolating circuit at the cycle of N/fs, M memories for storing M data which are held by the register at the cycle of N/fs, and controller for controlling data write/read operations of the memories at the cycle of M/fs and a selecter for selecting M data read from the memories by the controller successivly at the cycle of 1/fs.

公开(公告)号：US5146327A

公开(公告)日：1992-09-08

申请号：US598626

申请日：1990-10-11

申请人： Yoshio Sugimori ,  Yoshihide Kimata ,  Yoshihiko Ogawa ,  Kiyoyuki Kawai

发明人： Yoshio Sugimori ,  Yoshihide Kimata ,  Yoshihiko Ogawa ,  Kiyoyuki Kawai

IPC分类号： H04N7/00 ,  H04N7/015 ,  H04N7/08 ,  H04N7/081

CPC分类号： H04N7/015 ,  H04N7/007 ,  H04N7/08 ,  Y10S348/904

摘要： The present invention is ingeniously conceived for a transmission system for a first television signal so as to enable a first television signal of a wide aspect screen to be transmitted in one channel and the transmitted television signal to be reproduced on a receiver of a conventional aspect screen. To this end, a screen dividing circuit (12) divides a wide aspect screen signal into a center panel signal and side panel signals. The center panel signal is supplied via a delay circuit (13) to an adder (16). The side panel signals are so allocated as to provide horizontal and vertical signals. The horizontal side signal is supplied via a horizontal overscan multiplexing circuit 16 to the adder (16) where it is multiplexed on a horizontal overscan area of the center panel signal. In the vertical overscan multiplexing circuit, the vertical side signal is time compressed and reverse processed for each line to provide it in a continuous form. The output of a vertical overscan multiplexing circuit (20) is supplied to a switch (18) where it is time division multiplexed on vertical overscan areas of the center panel signal which is sent from the adder (16) via a delay circuit (17).

摘要翻译： PCT No.PCT / JP90 / 00136 Sec。 371 1990年10月11日第 102（e）1990年10月11日PCT PCT 1990年2月5日提交PCT公布。 出版物WO90 / 09719 日期1990年08月23日。本发明巧妙地构思了用于第一电视信号的传输系统，以便能够在一个信道中发送宽屏幕屏幕的第一电视信号，并将所发送的电视信号再现在 常规方面屏幕的接收器。 为此，屏幕分割电路（12）将宽屏幕屏幕信号分成中央面板信号和侧面板信号。 中央面板信号通过延迟电路（13）提供给加法器（16）。 侧面板信号如此分配，以提供水平和垂直信号。 水平侧信号通过水平过扫描多路复用电路16提供给加法器（16），在加法器16中多路复用在中央面板信号的水平过扫描区域上。 在垂直过扫描多路复用电路中，垂直方向信号对于每条线进行时间压缩和反向处理，以连续的形式提供。 垂直过扫描多路复用电路（20）的输出被提供给开关（18），在开关（18）上经由延迟电路（17）从加法器（16）发送的中心面板信号的垂直过扫描区域上进行时分复用， 。

公开(公告)号：US4903317A

公开(公告)日：1990-02-20

申请号：US66073

申请日：1987-06-23

申请人： Eitaro Nishihara ,  Zhixiong Wu ,  Yoshihiko Ogawa

发明人： Eitaro Nishihara ,  Zhixiong Wu ,  Yoshihiko Ogawa

IPC分类号： G06T9/00 ,  H04N7/26 ,  H04N7/28 ,  H04N7/50

CPC分类号： H04N19/94 ,  H04N19/17 ,  H04N19/61 ,  H04N19/30

摘要： An image processing apparatus includes a memory for storing image data, a loss-compression circuit for loss-compressing the image data, an expansion circuit for expanding the loss-compressed image data, and a difference circuit for calculating a difference between the original image data of the image memory and the expanded image data of the expansion circuit. A lossless compression circuit lossless-compresses the difference image data obtained by the difference circuit. A multiplexer multiplexes the loss-compressed image data output from the loss-compression circuit, with the lossless-compressed difference data obtained by the lossless-compression circuit.

摘要翻译： 图像处理装置包括存储图像数据的存储器，用于对图像数据进行损耗压缩的损耗压缩电路，扩展损失压缩图像数据的扩展电路，以及用于计算原始图像数据之间的差异的差分电路 的图像存储器和扩展电路的扩展图像数据。 无损压缩电路对由差分电路获得的差分图像数据进行无损压缩。 多路复用器将从损失压缩电路输出的损失压缩图像数据与由无损压缩电路获得的无损压缩差分数据进行多路复用。