公开(公告)号：US12025649B2

公开(公告)日：2024-07-02

申请号：US18226924

申请日：2023-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/26 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/2607 ,  G01R31/3177 ,  G01R31/318513 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318552 ,  G01R31/318594

Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

公开(公告)号：US20240061038A1

公开(公告)日：2024-02-22

申请号：US18386301

申请日：2023-11-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185 ,  H10K50/814 ,  H10K50/816 ,  H10K50/844 ,  H10K59/122 ,  H10K59/123 ,  H10K59/124 ,  H10K59/121 ,  H10K71/00 ,  G06F11/26 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/318555 ,  G01R31/318572 ,  H10K50/814 ,  H10K50/816 ,  H10K50/844 ,  H10K59/122 ,  H10K59/123 ,  H10K59/124 ,  H10K59/1213 ,  H10K71/00 ,  G06F11/26 ,  G01R31/31723 ,  G01R31/31727 ,  H10K59/1201

Abstract: In some examples, an integrated circuit comprises: a TDI input, a TDO output, a TCK input and a TMS input; a TAP state machine (TSM) having an input coupled to the TCK input, an input coupled to the TMS input, an instruction register control output, a TSM data register control (DRC) output, and a TSM state output; an instruction register having an input coupled to the TDI input, an output coupled to the TDO output, and a control input coupled to the instruction register control output of the TAP state machine; router circuitry including a TSM DRC input coupled to the TSM DRC output, a control DRC input coupled to the TSM state output, and a router DRC output; and a data register having an input coupled to the TDI input, an output coupled to the TDO output, and a data register DRC input coupled to the router DRC output.

公开(公告)号：US20240019489A1

公开(公告)日：2024-01-18

申请号：US18373447

申请日：2023-09-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G06F11/27 ,  G01R31/3185 ,  G01R31/3177 ,  G06F11/267

CPC classification number: G01R31/31723 ,  G06F11/27 ,  G01R31/31727 ,  G01R31/318572 ,  G01R31/3177 ,  G01R31/31722 ,  G01R31/31725 ,  G06F11/267 ,  G06F11/261

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

公开(公告)号：US11846673B2

公开(公告)日：2023-12-19

申请号：US18123406

申请日：2023-03-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318555 ,  G01R31/318563

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

公开(公告)号：US11762014B2

公开(公告)日：2023-09-19

申请号：US18094522

申请日：2023-01-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185 ,  G01R31/3183 ,  G01R31/28

CPC classification number: G01R31/31723 ,  G01R31/2896 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/318513 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318594

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

公开(公告)号：US20230273258A1

公开(公告)日：2023-08-31

申请号：US18313608

申请日：2023-05-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel ,  Baher S. Haroun

IPC: G01R31/3177 ,  G01R31/26 ,  G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/26 ,  G01R31/318505 ,  G01R31/318577 ,  G01R31/31723

Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

公开(公告)号：US11740286B2

公开(公告)日：2023-08-29

申请号：US17470500

申请日：2021-09-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/31727 ,  G01R31/318536 ,  G01R31/318572 ,  G01R31/318577

Abstract: Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

公开(公告)号：US20230258715A1

公开(公告)日：2023-08-17

申请号：US18305454

申请日：2023-04-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/31713 ,  G01R31/31723

Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.

公开(公告)号：US20230228814A1

公开(公告)日：2023-07-20

申请号：US18123406

申请日：2023-03-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177

CPC classification number: G01R31/3177

Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

公开(公告)号：US20230194603A1

公开(公告)日：2023-06-22

申请号：US18108720

申请日：2023-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Lee D. Whetsel

IPC: G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555

Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.