公开(公告)号：US11532633B2

公开(公告)日：2022-12-20

申请号：US17491201

申请日：2021-09-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Tushar Sharma ,  Tanmoy Roy ,  Shishir Kumar

IPC: G11C11/00 ,  H01L27/11 ,  G11C5/06 ,  G11C11/412 ,  H01L27/02 ,  G11C8/16 ,  G11C11/417

Abstract: The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.

公开(公告)号：US11531873B2

公开(公告)日：2022-12-20

申请号：US16909673

申请日：2020-06-23

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Thomas Boesch ,  Giuseppe Desoli ,  Surinder Pal Singh ,  Carmine Cappetta

IPC: G06N3/063 ,  G06F9/50 ,  H03M7/30

Abstract: Techniques and systems are provided for implementing a convolutional neural network. One or more convolution accelerators are provided that each include a feature line buffer memory, a kernel buffer memory, and a plurality of multiply-accumulate (MAC) circuits arranged to multiply and accumulate data. In a first operational mode the convolutional accelerator stores feature data in the feature line buffer memory and stores kernel data in the kernel data buffer memory. In a second mode of operation, the convolutional accelerator stores kernel decompression tables in the feature line buffer memory.

公开(公告)号：US11520721B2

公开(公告)日：2022-12-06

申请号：US16933752

申请日：2020-07-20

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

Inventor： Nirav Prashantkumar Trivedi ,  Sandip Atal ,  Rolf Nandlinger

IPC: G06F13/00 ,  G06F13/28 ,  H03M1/38 ,  H03M1/12

Abstract: A digital interface circuit includes a queue block configured to be coupled between an analog-to-digital converter (ADC) and a Direct Memory Access (DMA) controller of a processor, where the queue block comprises a command buffer and is configured to: receive a first command from the DMA controller; store the first command in the command buffer; modify the first command in accordance with first control bits of the first command to generate a modified first command; and send the modified first command to the ADC.

公开(公告)号：US11513883B2

公开(公告)日：2022-11-29

申请号：US17161832

申请日：2021-01-29

Applicant: STMicroelectronics International N.V.

Inventor： Charul Jain ,  Asif Rashid Zargar

IPC: G06F11/07

Abstract: An apparatus includes a primary processor and a secondary processor configured to receive a first signal, a second signal and a plurality of input signals, and perform same operations as each other based on the first signal, the second signal and the plurality of input signals, a comparison circuit configured to receive output signals of the primary processor and the secondary processor, and detect a lockstep mismatch between the primary processor and the secondary processor based on the output signals, a fault capturing circuit configured to receive the first signal and the second signal, and capture a fault signal generated by the comparison circuit, and a first glitch absorption device configured to receive the first signal and the second signal, and absorb glitches fed into the first glitch absorption device.

公开(公告)号：US11513544B1

公开(公告)日：2022-11-29

申请号：US17537010

申请日：2021-11-29

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Mayankkumar Hareshbhai Niranjani ,  Dhulipalla Phaneendra Kumar ,  Gourav Garg ,  Sourabh Banzal

IPC: G05F1/10 ,  G05F3/02 ,  G05F1/46 ,  H03K19/20

Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.

公开(公告)号：US11507831B2

公开(公告)日：2022-11-22

申请号：US16799671

申请日：2020-02-24

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Surinder Pal Singh ,  Thomas Boesch ,  Giuseppe Desoli

IPC: G06N3/08 ,  G06F17/18 ,  G06K9/62 ,  G06N3/04

Abstract: A convolutional neural network includes a pooling unit. The pooling unit performs pooling operations between convolution layers of the convolutional neural network. The pooling unit includes hardware blocks that promote computational and area efficiency in the convolutional neural network.

公开(公告)号：US11502659B2

公开(公告)日：2022-11-15

申请号：US16903552

申请日：2020-06-17

Applicant: STMicroelectronics International N.V.

Inventor： Riju Biswas

IPC: H03G3/30 ,  G01S13/931 ,  H03F3/45

Abstract: Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-zero cancelation to yield a desired transfer function without gain peaking at a bandwidth in which attenuation is desired, and utilizes a low pass filter effectively formed by a feedback loop including a high pass filter and a differential amplifier to ensure the desired level of attenuation at the desired bandwidth. In some instances, a chopper may be utilized in the feedback loop prior to the high pass filter, and after the differential amplifier, so as to reduce the bandwidth of the differential amplifier in the feedback loop.

公开(公告)号：US20220352817A1

公开(公告)日：2022-11-03

申请号：US17866372

申请日：2022-07-15

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

IPC: H02M3/07

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

公开(公告)号：US20220345149A1

公开(公告)日：2022-10-27

申请号：US17723225

申请日：2022-04-18

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Abhishek JAIN ,  Sharad GUPTA

IPC: H03M3/00

Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

公开(公告)号：US20220334865A1

公开(公告)日：2022-10-20

申请号：US17657856

申请日：2022-04-04

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

Inventor： Roberto Colombo ,  Vivek Mohan Sharma

IPC: G06F9/455 ,  G06F11/07

Abstract: A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.