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公开(公告)号：US10854499B2
公开(公告)日：2020-12-01
申请号：US15643825
申请日：2017-07-07
Inventor： Jung-Chan Yang , Ting-Wei Chiang , Cheng-I Huang , Hui-Zhong Zhuang , Chi-Yu Lu , Stefan Rusu
IPC: G06F30/394 , H01L21/76 , H01L23/528 , H03K19/094 , H01L23/522
Abstract: An integrated circuit structure includes a set of rails, a first and second set of conductive structures and a first set of vias. The set of rails extends in a first direction and is located at a first level. Each rail of the set of rails is separated from one another in a second direction. The first set of conductive structures extends in the second direction, overlaps the set of rails and is located at a second level. The first set of vias is between the set of rails and the first set of conductive structures. Each of the first set of vias is located where each of the first set of conductive structures overlaps each of the set of rails. The first set of vias couple the first set of conductive structures to the set of rails. The second set of conductive structures is between the set of rails.
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公开(公告)号：US10740531B2
公开(公告)日：2020-08-11
申请号：US15792289
申请日：2017-10-24
Inventor： Jung-Chan Yang , Ting-Wei Chiang , Jerry Chang-Jui Kao , Hui-Zhong Zhuang , Lee-Chung Lu , Li-Chun Tien , Meng-Hung Shen , Shang-Chih Hsieh , Chi-Yu Lu
IPC: G06F30/394 , H01L27/118 , H01L23/522 , H01L23/528 , H01L27/02
Abstract: An integrated circuit structure includes a set of gate structures, a first conductive structure, a first and second set of vias, and a first set of conductive structures. The set of gate structures is located at a first level. The first conductive structure extends in a first direction, overlaps the set of gate structures and is located at a second level. The first set of vias is between the set of gate structures and the first conductive structure. The first set of vias couple the set of gate structures to the first conductive structure. The first set of conductive structures extend in a second direction, overlap the first conductive structure, and is located at a third level. The second set of vias couple the first set of conductive structures to the first conductive structure, and is between the first set of conductive structures and the first conductive structure.
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公开(公告)号：US10685162B2
公开(公告)日：2020-06-16
申请号：US16228530
申请日：2018-12-20
Inventor： Cheok-Kei Lei , Yu-Chi Li , Chia-Wei Tseng , Zhe-Wei Jiang , Chi-Lin Liu , Jerry Chang-Jui Kao , Jung-Chan Yang , Chi-Yu Lu , Hui-Zhong Zhuang
IPC: G06F30/392 , G06F30/394 , G06F30/398
Abstract: A layout of an integrated circuit includes: a first layout device; a second layout device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein the second layout device is a redundant circuit in the integrated circuit; a conductive path disposed across the boundary of the first layout device and the second layout device; and a cut layer disposed on the conductive path and nearby the boundary for disconnecting the first layout device from the second layout device by cutting the conductive path into a first conductive portion and a second conductive portion according to a position of the cut layer; wherein the first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.
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公开(公告)号：US10678977B2
公开(公告)日：2020-06-09
申请号：US16186788
申请日：2018-11-12
Inventor： Mao-Wei Chiu , Ting-Wei Chiang , Hui-Zhong Zhuang , Li-Chun Tien , Chi-Yu Lu
IPC: G06F30/30 , G06F30/392 , G06F30/39 , H01L27/02 , G06F30/398 , H01L23/528 , G06F30/394 , G06F115/08
Abstract: A semiconductor device including: standard functional cells located in a logic area; standard spare cells arranged in a spare region of the logic area; and a metallization layer including segments, some of the segments being included in corresponding ones of the functional cells, some of the segments being included in corresponding ones of the spare cells, and some of the segments representing strap lines; and wherein a first pitch of the standard spare cells is based on a second pitch of the strap lines.
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公开(公告)号：US20200075476A1
公开(公告)日：2020-03-05
申请号：US16676175
申请日：2019-11-06
Inventor： Tung-Heng Hsieh , Ting-Wei Chiang , Chung-Te Lin , Hui-Zhong Zhuang , Li-Chun Tien , Sheng-Hsiung Wang
IPC: H01L23/528 , H01L23/535 , H01L27/088 , H01L29/40 , H01L21/768 , H01L21/8234 , H01L23/485
Abstract: A semiconductor device includes a substrate having an active region, a first gate structure over a top surface of the substrate, a second gate structure over the top surface of the substrate, a pair of first spacers on each sidewall of the first gate structure, a pair of second spacers on each sidewall of the second gate structure, an insulating layer over at least the first gate structure, a first conductive feature over the active region and a second conductive feature over the substrate. Further, the second gate structure is adjacent to the first gate structure and a top surface of the first conductive feature is coplanar with a top surface of the second conductive feature.
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Patent Agency Ranking
公开(公告)号：US10553575B2
公开(公告)日：2020-02-04
申请号：US15815289
申请日：2017-11-16
Inventor： Li-Chun Tien , Ya-Chi Chou , Hui-Zhong Zhuang , Chun-Fu Chen , Ting-Wei Chiang , Hsiang Jen Tseng
IPC: H01L27/02 , H01L27/118 , G06F17/50
Abstract: A semiconductor device includes an array of Engineering Change Order (ECO) cells. Each of the ECO cells in the array includes a first metal pattern and a second metal pattern. Each of the ECO cells in the array further includes a plurality of active area patterns isolated from each other and arranged between the first and second metal patterns. Each of the ECO cells in the array further includes a first central metal pattern overlapping the first metal pattern. Each of the ECO cells in the array further includes a via electrically connecting the first central metal pattern to the first metal pattern. The plurality of active area patterns is arranged symmetrically about the first central metal pattern.
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公开(公告)号：US20190341387A1
公开(公告)日：2019-11-07
申请号：US16515709
申请日：2019-07-18
Inventor： Pochun Wang , Ting-Wei Chiang , Chih-Ming Lai , Hui-Zhong Zhuang , Jung-Chan Yang , Ru-Gun Liu , Shih-Ming Chang , Ya-Chi Chou , Yi-Hsiung Lin , Yu-Xuan Huang , Guo-Huei Wu , Yu-Jung Chang
IPC: H01L27/108 , H01L27/02 , H01L23/528 , H01L21/768 , H01L23/522
Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
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188.发明授权公开(公告)号：US10289789B2
公开(公告)日：2019-05-14
申请号：US15601697
申请日：2017-05-22
Inventor： Shang-Chih Hsieh , Hui-Zhong Zhuang , Ting-Wei Chiang , Chun-Fu Chen , Hsiang-Jen Tseng
IPC: G06F17/50 , H01L27/02 , H01L21/768 , H01L27/118
Abstract: An integrated circuit designing system includes a non-transitory storage medium and a hardware processor. The non-transitory storage medium is encoded with a layout of a standard cell corresponding to a predetermined manufacturing process. The predetermined manufacturing process has a nominal minimum pitch, along a predetermined direction, of metal lines. The layout of the standard cell has a cell height along the predetermined direction, and the cell height is a non-integral multiple of the nominal minimum pitch. The hardware processor communicatively coupled with the non-transitory storage medium and configured to execute a set of instructions for generating an integrated circuit layout based on the layout of the standard cell and the nominal minimum pitch.
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公开(公告)号：US20180253522A1
公开(公告)日：2018-09-06
申请号：US15971646
申请日：2018-05-04
Inventor： Tung-Heng Hsieh , Sheng-Hsiung Wang , Hui-Zhong Zhuang , Yu-Cheng Yeh , Tsung-Chieh Tsai , Juing-Yi Wu , Liang-Yao Lee , Jyh-Kang Ting
IPC: G06F17/50 , H01L27/02 , H01L27/118
Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.
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190.发明授权公开(公告)号：US09991158B2
公开(公告)日：2018-06-05
申请号：US14484670
申请日：2014-09-12
Inventor： Tung-Heng Hsieh , Hui-Zhong Zhuang , Chung-Te Lin , Sheng-Hsiung Wang , Ting-Wei Chiang , Li-Chun Tien , Tsung-Chieh Tsai
IPC: H01L21/28 , H01L21/768 , H01L27/02 , H01L21/8234 , H01L27/088 , H01L21/265
CPC classification number: H01L21/76877 , H01L21/2658 , H01L21/28008 , H01L21/76829 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L21/823475 , H01L27/0207 , H01L27/088
Abstract: A semiconductor device includes a substrate having an active area, a gate structure over the active area, a lower conductive layer over and electrically coupled to the active area, and an upper conductive layer over and electrically coupled to the lower conductive layer. The lower conductive layer is at least partially co-elevational with the gate structure. The lower conductive layer includes first and second conductive segments spaced from each other. The upper conductive layer includes a third conductive segment overlapping the first and second conductive segments. The third conductive segment is electrically coupled to the first conductive segment, and electrically isolated from the second conductive segment.
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