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公开(公告)号：US12125792B2
公开(公告)日：2024-10-22
申请号：US18128742
申请日：2023-03-30
发明人： Jung-Chan Yang , Chi-Yu Lu , Hui-Zhong Zhuang , Chih-Liang Chen
IPC分类号： H01L23/535 , H01L21/768 , H01L21/8234 , H01L23/522 , H01L23/528 , H01L23/538 , H01L27/02 , H01L29/40 , H01L29/417
CPC分类号： H01L23/535 , H01L21/76895 , H01L21/823475 , H01L23/5221 , H01L23/528 , H01L23/5286 , H01L23/5386 , H01L27/0207 , H01L29/401 , H01L29/41725
摘要： A method of forming a semiconductor device, includes forming an active region; forming first, second and third metal-to-drain/source (MD) contact structures which extend in a first direction, and correspondingly overlap and electrically couple to the active region; forming a via-to-via (V2V) rail which extends in a second direction perpendicular to the first direction, overlaps at least the first MD contact structure and the third MD contact structures; forming a first via-to-MD (VD) structure over, and electrically coupled to, the first MD contact structure and the V2V rail; and forming a first conductive segment which overlaps the V2V rail, is in a first metallization layer, and is electrically coupled to the first VD structure.
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公开(公告)号：US11983479B2
公开(公告)日：2024-05-14
申请号：US17885118
申请日：2022-08-10
发明人： Jung-Chan Yang , Ting-Wei Chiang , Jerry Chang-Jui Kao , Hui-Zhong Zhuang , Lee-Chung Lu , Li-Chun Tien , Meng-Hung Shen , Shang-Chih Hsieh , Chi-Yu Lu
IPC分类号： G06F30/394 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/118
CPC分类号： G06F30/394 , H01L23/5226 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2027/11887
摘要： A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.
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公开(公告)号：US11552069B1
公开(公告)日：2023-01-10
申请号：US17463241
申请日：2021-08-31
IPC分类号： H01L27/02 , G06F1/3287
摘要： An integrated circuit includes a first, second and third power rail, and a header circuit coupled to a gated circuit. The gated circuit is configured to operate on a first or second voltage. The first and second power rail are on a back-side of a wafer, and extend in a first direction. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The second power rail is separated from the first power rail in a second direction. The second power rail is configured to supply the second voltage to the gated circuit. The third power rail is on a front-side of the wafer and includes a first set of conductors extending in the second direction, and separated in the first direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit.
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公开(公告)号：US11508661B2
公开(公告)日：2022-11-22
申请号：US16936249
申请日：2020-07-22
发明人： Pochun Wang , Ting-Wei Chiang , Chih-Ming Lai , Hui-Zhong Zhuang , Jung-Chan Yang , Ru-Gun Liu , Ya-Chi Chou , Yi-Hsiung Lin , Yu-Xuan Huang , Yu-Jung Chang , Guo-Huei Wu , Shih-Ming Chang
IPC分类号： H01L23/48 , H01L23/535 , H01L21/768 , H01L27/088 , H01L27/092 , H01L21/8238 , G06F30/39 , G06F30/392
摘要： An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
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公开(公告)号：US11074390B2
公开(公告)日：2021-07-27
申请号：US16512062
申请日：2019-07-15
发明人： Chien-Hsing Li , Ting-Wei Chiang , Jung-Chan Yang , Ting Yu Chen
IPC分类号： G06F30/394 , G06F30/392
摘要： A method includes reserving a routing track within a cell, the cell includes signal lines for connection to elements within the cell, the cell further includes a plurality of routing tracks, the reserved routing track is one of the plurality of routing tracks, and the reserved routing track is free of the signal lines. The method includes placing the cell in a chip-level layout, wherein the chip-level layout includes a plurality of power rails. The method includes determining whether any of the plurality of power rails overlaps with any of the plurality of routing tracks other than the reserved routing track. The method includes adjusting a position of the cell in the chip-level layout in response to a determination that at least one power rail of the plurality of power rails overlaps with at least one routing track of the plurality of routing tracks other than the reserved routing track.
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公开(公告)号：US12033998B2
公开(公告)日：2024-07-09
申请号：US18363230
申请日：2023-08-01
IPC分类号： H01L27/02 , G06F1/3287
CPC分类号： H01L27/0207 , G06F1/3287
摘要： An integrated circuit includes a gated circuit configured to operate on at least a first or a second voltage, a header circuit coupled to the gated circuit, a first and second power rail on a back-side of a wafer, and a third power rail on a front-side of the wafer. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The first power rail includes a first portion, a second portion and a third portion, the third portion being between the first portion and the second portion. The second power rail is configured to supply the second voltage to the gated circuit, and is between the first portion and the second portion. The third power rail includes a first set of conductors. Each of the first set of conductors being configured to supply a third voltage to the header circuit.
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公开(公告)号：US11756999B2
公开(公告)日：2023-09-12
申请号：US17205670
申请日：2021-03-18
IPC分类号： H01L29/06 , H01L27/092 , H01L27/02 , H01L21/033 , H01L29/66 , H01L29/78 , H01L21/8238 , G06F30/392
CPC分类号： H01L29/0696 , G06F30/392 , H01L21/0337 , H01L21/823821 , H01L27/0207 , H01L27/0924 , H01L29/6681 , H01L29/66545 , H01L29/7851
摘要： In at least one cell region, a semiconductor device includes fin patterns and at least one overlying gate structure. The fin patterns (dummy and active) are substantially parallel to a first direction. Each gate structure is substantially parallel to a second direction (which is substantially perpendicular to the first direction). First and second active fin patterns have corresponding first and second conductivity types. Each cell region, relative to the second direction, includes: a first active region which includes a sequence of three or more consecutive first active fin patterns located in a central portion of the cell region; a second active region which includes one or more second active fin patterns located between the first active region and a first edge of the cell region; and a third active region which includes one or more second active fin patterns located between the first active region and a second edge of the cell region.
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公开(公告)号：US11636248B2
公开(公告)日：2023-04-25
申请号：US17237484
申请日：2021-04-22
发明人： Jung-Chan Yang , Ting Yu Chen , Li-Chun Tien , Fong-Yuan Chang
IPC分类号： G06F30/392 , G06F30/394
摘要： An IC layout diagram generation system includes a processor and a non-transitory, computer readable storage medium including computer program code for one or more programs. The non-transitory, computer readable storage medium and the computer program code are configured to, with the processor, cause the system to align a border segment of a cell at a predetermined location relative to a plurality of second metal layer tracks, position the cell relative to a first metal layer cut region alignment pattern based on the plurality of second metal layer tracks, overlap the cell with a first metal layer cut region based on the first metal layer cut region alignment pattern, and generate an IC layout diagram of an IC device based on the cell and the first metal layer cut region.
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公开(公告)号：US11302787B2
公开(公告)日：2022-04-12
申请号：US16580779
申请日：2019-09-24
IPC分类号： H01L29/41 , H01L29/417 , H01L29/78 , H01L29/08
摘要： A semiconductor device includes an active region in a substrate. The active region extends in a first direction. The semiconductor device further includes a gate structure extending in a second direction different from the first direction. The gate structure extends across the active region. The semiconductor device further includes a plurality of source/drain contacts extending in the second direction and overlapping a plurality of source/drain regions in the active region on opposite sides of the gate structure. A first source/drain contact of the plurality of source/drain contacts has a first width, and a second source/drain contact of the plurality of source/drain contacts has a second width less than the first width.
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公开(公告)号：US11004855B2
公开(公告)日：2021-05-11
申请号：US16515709
申请日：2019-07-18
发明人： Pochun Wang , Ting-Wei Chiang , Chih-Ming Lai , Hui-Zhong Zhuang , Jung-Chan Yang , Ru-Gun Liu , Shih-Ming Chang , Ya-Chi Chou , Yi-Hsiung Lin , Yu-Xuan Huang , Guo-Huei Wu , Yu-Jung Chang
IPC分类号： H01L27/108 , H01L29/78 , H01L21/8238 , H01L27/092 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/02
摘要： An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.
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