公开(公告)号：US20250021736A1

公开(公告)日：2025-01-16

申请号：US18785611

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Yeh Yu ,  Wei-Yi Hu ,  Shih-Hsuan Chien ,  You-Cheng Xiao ,  Ya-Chi Chou

IPC: G06F30/392 ,  G06F30/394 ,  H10B10/00

Abstract: A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.

公开(公告)号：US20230289508A1

公开(公告)日：2023-09-14

申请号：US17852985

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chi-Yeh Yu ,  Wei-Yi Hu ,  Shih-Hsuan Chien ,  You-Cheng Xiao ,  Ya-Chi Chou

IPC: G06F30/392 ,  G06F30/394 ,  H01L27/11

CPC classification number: G06F30/392 ,  G06F30/394 ,  H01L27/11

Abstract: A device including functional blocks and dummy cells. The functional blocks include a first functional block and a second functional block. Each dummy cell having a cell boundary defined by non-functioning active areas and non-functioning gates for filling space between the functional blocks and including a dummy cell configured to be situated between the first functional block and the second functional block such that the dummy cell directly abuts each of the first functional block and the second functional block.

公开(公告)号：US11004855B2

公开(公告)日：2021-05-11

申请号：US16515709

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Guo-Huei Wu ,  Yu-Jung Chang

IPC: H01L27/108 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US20190067290A1

公开(公告)日：2019-02-28

申请号：US15691974

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Yu-Jung Chang ,  Guo-Huei Wu

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528

CPC classification number: H01L27/10823 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.

公开(公告)号：US20230369320A1

公开(公告)日：2023-11-16

申请号：US18182657

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ya-Chi Chou ,  Wei-Ling Chang ,  Wei-Ren Chen ,  Chi-Yu Lu

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L27/088 ,  H01L27/092 ,  H01L21/76224

Abstract: A device includes a substrate, a first well region, a second well region, and a dummy region in the substrate, where the dummy region is a non-functional region situated between the first well region and the second well region. The first well region is configured to receive a first voltage and the second well region is configured to receive a second voltage that is different than the first voltage. The device further includes an active region that extends through at least part of the first well region and at least part of the dummy region, and at least one isolation structure situated in the dummy region between a first gate structure that extends over the active region in the dummy region on one side of the at least one isolation structure and a second gate structure on another side of the at least one isolation structure.

公开(公告)号：US11508661B2

公开(公告)日：2022-11-22

申请号：US16936249

申请日：2020-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Yu-Jung Chang ,  Guo-Huei Wu ,  Shih-Ming Chang

IPC: H01L23/48 ,  H01L23/535 ,  H01L21/768 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  G06F30/39 ,  G06F30/392

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

公开(公告)号：US10796060B2

公开(公告)日：2020-10-06

申请号：US16386838

申请日：2019-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Fong-Yuan Chang ,  Li-Chun Tien ,  Shun-Li Chen ,  Ya-Chi Chou ,  Ting-Wei Chiang ,  Po-Hsiang Huang

IPC: G06F30/394 ,  G06F30/392 ,  G06F30/398 ,  G06F119/18

Abstract: A computer readable storage medium encoded with program instructions, wherein, when the program instructions is executed by at least one processor, the at least one processor performs a method. The method includes selecting a cell, determining whether a pin has an area smaller than a predetermined area, allowing a pin access of the pin to extend in a corresponding patterning track of the pin access when the pin access when the pin is determined to be having an area smaller than the predetermined threshold, and causing an integrated circuit to be fabricated according to the pin.

公开(公告)号：US09831230B2

公开(公告)日：2017-11-28

申请号：US13965648

申请日：2013-08-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Li-Chun Tien ,  Ya-Chi Chou ,  Hui-Zhong Zhuang ,  Chun-Fu Chen ,  Ting-Wei Chiang ,  Hsiang Jen Tseng

IPC: G06F17/50 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L27/0207 ,  G06F17/5068 ,  H01L27/11807 ,  H01L2027/11875

Abstract: A layout of a standard cell is stored on a non-transitory computer-readable medium and includes a first conductive pattern, a second conductive pattern, a plurality of active area patterns and a first central conductive pattern. The plurality of active area patterns is isolated from each other and arranged in a first row and a second row between the first and second conductive patterns. The first row is adjacent the first conductive pattern and includes a first active area pattern and a second active area pattern among the plurality of active area patterns. The second row is adjacent the second conductive pattern and includes a third active area pattern and a fourth active area pattern among the plurality of active area patterns. The first central conductive pattern is arranged between the first and second active area patterns. The first central conductive pattern overlaps the first conductive pattern.

公开(公告)号：US10734321B2

公开(公告)日：2020-08-04

申请号：US16135684

申请日：2018-09-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Yu-Jung Chang ,  Guo-Huei Wu ,  Shih-Ming Chang

IPC: H01L29/40 ,  H01L23/535 ,  H01L21/768 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8238 ,  G06F30/39 ,  G06F30/392

Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.

公开(公告)号：US10446555B2

公开(公告)日：2019-10-15

申请号：US15691974

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pochun Wang ,  Ting-Wei Chiang ,  Chih-Ming Lai ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Ru-Gun Liu ,  Shih-Ming Chang ,  Ya-Chi Chou ,  Yi-Hsiung Lin ,  Yu-Xuan Huang ,  Yu-Jung Chang ,  Guo-Huei Wu

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

Abstract: An integrated circuit includes a semiconductor substrate, an isolation region extending into, and overlying a bulk portion of, the semiconductor substrate, a buried conductive track comprising a portion in the isolation region, and a transistor having a source/drain region and a gate electrode. The source/drain region or the gate electrode is connected to the buried conductive track.